MIMX.RT685 power sequencing

leduclong — Mon, 30 Jan 2023 04:39:53 GMT

Hi,

I would like to consult you about the valid power sequencing of iMX.RT685.

From the data sheet:

Following power-on sequence should be followed when using an external PMIC or external IC to drive the VDDCORE pin (internal LDO is disabled, see timing diagram below):
1. VDD_AO1V8, VDD1V8, and VDD1V8_1 pins should be powered first. There is no
power sequence requirement between powering the VDD_AO1V8 and VDD1V8 pins.

2. VDDA_ADC1V8 and VREFP can be powered concurrently with VDD_AO1V8 and
VDD1V8 or later.

3. VDDIO_x and VDDA_BIAS pins can be powered concurrently with VDD_AO1V8 and
VDD1V8 if these pins are 1.8 V range or later if these pins are 3.3 V range. If the
VDDIO_x is not powered concurrently with the VDD1V8, the delta voltage between
VDDIO_x and VDD1V8 must be 1.89 V or less.

4. Power up the VDDCORE. The external RESETN should be held low until VDDCORE
is valid in the timing diagram.VDDCORE should not be ramped up until after all the
other supplies have completed ramp up.

Will the following power sequence work?

1. Power up the VDD1V8, VDD1V8_1, VDDIO_0 and VDDIO_2 (both at 1.8V)

2. Power up VDDAO_1V8

3. Power up VDDIO_1 at 1V8 (later to be changed to 2V8)

4. Power up VDDCORE at 1V0

5. Release the RESETn

Thank you for your support.

Re: MIMX.RT685 power sequencing

jingpan — Mon, 06 Feb 2023 07:37:32 GMT

Hi @leduclong ,

Seems fine.

Regards,

Jing

topic Re: MIMX.RT685 power sequencing in i.MX Processors

MIMX.RT685 power sequencing

Re: MIMX.RT685 power sequencing