i.MX ProcessorsのトピックRe: iMX6Q IPU Double-buffering

iMX6Q IPU Double-buffering

ogj — Wed, 18 Jan 2023 04:28:46 GMT

I’m using an iMX6Q processor (bare metal build) and am trying to determine the correct usage of the IPU_CH_BUF0_RDY and IPU_CH_BUF1_RDY bits in the IPU. I’m using a single buffer for a (static) background (IDMA ch 23), and double –buffering the foreground (ch 27). Now let’s say I’m displaying BUF0 (EBA0), IPU_CH_BUF0_RDY0:27 is 1, IPU_CUR_BUF:27 is 0, and I’m updating BUF1 (EBA1). It takes me several display refresh cycles (@ 60 per secs), say 60ms, to update BUF1 with new data. Now I want to switch over to display BUF1 (and then update BUF0) – which of course is the purpose of double buffering. If I now set IPU_CH_BUF1_RDY0:27 to 1, will this cause a switch to display BUF1 at the next EOF (so I can update BUF0)? I can’t clear IPU_CH_BUF0_RDY:27 using software, so how does it get cleared if the displays are swapped?

I tried playing around with the registers using a probe. I can set IPU_CH_BUF0_RDY0:27 fine. I thought if I then set IPU_CH_BUF1_RDY0:27, that it would clear IPU_CH_BUF0_RDY0:27, but it doesn’t, both bits remain set. This is with the IPU not running, so things may be different when it’s active. Any insight?

Re: iMX6Q IPU Double-buffering

Bio_TICFSL — Wed, 18 Jan 2023 14:53:36 GMT

Hello,

You can read the Mx6 reference manual for more information and you can how it is on current driver in yocto BSP.

Regards

Re: iMX6Q IPU Double-buffering

ogj — Wed, 25 Jan 2023 15:34:30 GMT

This is not acceptable answer. This is what the RM says:

When double buffering is used, the EBA0 is the base address of the buffer 0 and the EBA1 is the base address of the buffer 1. The IPU_CHA_CUR_BUF Register is a status register. It contains 1-bit pointers to the current working buffers for all IPU DMA channels. The IPU automatically toggles a pointer after completion of the current buffer processing. If the ARM platform is a data source for specific double-buffered channel, it should check this status bit in order to know what is the IPU current buffer. The ARM
platform is allowed to write to the buffer only when a working DMA channel does not use it. After the ARM platform has been fill the buffer, it has to set the corresponding bit in the IPU_CHA_BUF0_RDY and IPU_CHA_BUF1_RDY Registers. If needed, the ARM platform can only clear the pointer by writing 1 but not set it.