topic Re: PRE_PERIPH MUX in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/PRE-PERIPH-MUX/m-p/241117#M20056 <HTML><HEAD></HEAD><BODY><P>Hi, Johan</P><P>&nbsp;&nbsp;&nbsp;&nbsp; The pre_periph2 in CCM_CBCMR[22:21] is to select clock source for periph2_clk, it is for mmdc_ch1_axi_clk_root, the pre_periph in CCM_CBCMR[19:18] is to select clock source for periph_clk, and mmdc_ch0_axi_clk_root is sourcing from periph_clk, you can refer to the clock tree in i.MX6Q RM Figure 18-5 in CCM chapter. These are two different clock mux for different clock path.</P></BODY></HTML> Wed, 04 Dec 2013 11:59:21 GMT AnsonHuang 2013-12-04T11:59:21Z PRE_PERIPH MUX https://community.nxp.com/t5/i-MX-Processors/PRE-PERIPH-MUX/m-p/241116#M20055 <HTML><HEAD></HEAD><BODY><P><SPAN style="font-size: 10.0pt; font-family: 'Arial','sans-serif';">Normally the DDR clock are sourced via PLL2 – PFD2 and this source passes the PRE_PERIPH mux. The question is how the sub CCM register CCM_CBCMR are naming this mux. The pre_periph2 seams [22:21] to correspond to PFD2 but the question if it or pre_periph [19:18] should be used instead or both??</SPAN></P></BODY></HTML> Tue, 03 Dec 2013 13:45:22 GMT https://community.nxp.com/t5/i-MX-Processors/PRE-PERIPH-MUX/m-p/241116#M20055 mrlantz 2013-12-03T13:45:22Z Re: PRE_PERIPH MUX https://community.nxp.com/t5/i-MX-Processors/PRE-PERIPH-MUX/m-p/241117#M20056 <HTML><HEAD></HEAD><BODY><P>Hi, Johan</P><P>&nbsp;&nbsp;&nbsp;&nbsp; The pre_periph2 in CCM_CBCMR[22:21] is to select clock source for periph2_clk, it is for mmdc_ch1_axi_clk_root, the pre_periph in CCM_CBCMR[19:18] is to select clock source for periph_clk, and mmdc_ch0_axi_clk_root is sourcing from periph_clk, you can refer to the clock tree in i.MX6Q RM Figure 18-5 in CCM chapter. These are two different clock mux for different clock path.</P></BODY></HTML> Wed, 04 Dec 2013 11:59:21 GMT https://community.nxp.com/t5/i-MX-Processors/PRE-PERIPH-MUX/m-p/241117#M20056 AnsonHuang 2013-12-04T11:59:21Z