i.MX8 ECSPI1 and TLB SLB9670

tbriggs6 — Fri, 06 Jan 2023 20:41:58 GMT

Hello, I am trying to integrate an Infineon TPM SLB9670 into an i.MX8MP system. The TPM is connected via ECSPI1 and is the only device on that bus. The Linux kernel is 5.4.188 through Yocto Dunfell. The TPM device driver fails to initialize. I added some printk's, and see that during tpm_tis_spi_probe(), it invokes tpm_tis_core_init(), an SPI transfer is started, and sometimes fails with error -110. This corresponds to an ETIMEOUT, and is caused by the spi transfer failing after 50 attempts. After that, the tpm_tis_core_init returns an error -19, and the TPM does not initialize:

[ 5.109788] tpm: tpm_tis_spi_probe
[ 5.109809] tpm: tpm_tis_spi_transfer start addr=0 len=1
[ 5.110840] tpm: tpm_tis_spi_transfer fin=-110
[ 5.110845] tpm: tpm_tis_spi_transfer start addr=8 len=4
[ 5.110934] tpm: tpm_tis_spi_transfer fin=0
[ 5.110936] tpm: tpm_tis_spi_transfer start addr=8 len=4
[ 5.111850] tpm: tpm_tis_spi_transfer fin=-110
[ 5.111853] tpm: tpm_tis_core_init returned -19

I added mod wire to the SS0 and clock lines and used an o-scope. It looks right (SS0 drops, there is a delay, and then the i.MX8 runs the clock, and then SS0 is released back up). Note that the SS0 is pulled-up by the NXP (see pin mux below).

I followed guidance in these forums and disabled the DMA in the .dtsi and can see that its no longer listed in the /sys/devicetree entries. I also dropped the clock - the iMX8 is using an 80MHz clock, the SLB9670 is powered by 1.8V, so it should run less than 25MHz, and the slowest possible clock is achieved with a pre-scalar of 7, so 11.4 MHz.

The Linux config (from /proc/config.gz):
root@imx8mplus:/tmp# grep TPM config
CONFIG_TCG_TPM=y
CONFIG_HW_RANDOM_TPM=y
# CONFIG_TCG_VTPM_PROXY is not set
# CONFIG_TCG_FTPM_TEE is not set
# CONFIG_MFD_STPMIC1 is not set
# CONFIG_PWM_IMX_TPM is not set

The TPM is connected via the ECSPI1 bus as shown:

There are three parts of the device tree:

imx8mp.dtsi:

ecspi1: spi@30820000 {

#address-cells = <1>;

#size-cells = <0>;

compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";

reg = <0x30820000 0x10000>;

interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,

<&clk IMX8MP_CLK_ECSPI1_ROOT>;

clock-names = "ipg", "per";

assigned-clock-rates = <80000000>;

assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;

assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;

// per https://community.nxp.com/t5/i-MX-Processors/TPM-SLB9670-initialization-failed-on-i-MX8-ECSPI2/m-p/1003715/thread-id/148763

// dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;

// dma-names = "rx", "tx";

status = "disabled";

};

imx8mp-product.dts

&ecspi1 {

#address-cells = <1>;

#size-cells = <0>;

fsl,spi-num-chipselects = <1>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;

cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;

status = "okay";

tpm0:spi@0 {

reg = <0>;

compatible = "infineon,slb9670";

spi-max-frequency = <11428571>;

status = "okay";

};

And later, in the .dts, the pinmux:

pinctrl_ecspi1: ecspi1grp {

fsl,pins = <

MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82

MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82

MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82

};

pinctrl_ecspi1_cs: ecspi1cs {

fsl,pins = <

MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x146

};

Re: i.MX8 ECSPI1 and TLB SLB9670

jimmychan — Mon, 16 Jan 2023 08:57:41 GMT

Have you check the signal MOSI and MISO?

topic i.MX8 ECSPI1 and TLB SLB9670 in i.MX Processors

i.MX8 ECSPI1 and TLB SLB9670

Re: i.MX8 ECSPI1 and TLB SLB9670