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    <title>topic Re: I.MX8MN Cortex M7 SPI problem in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/I-MX8MN-Cortex-M7-SPI-problem/m-p/1578171#M199631</link>
    <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Have you tried one of the ECSPI examples available in the i.MX SDK?&lt;BR /&gt;Also, from the description it seems that the slave is having some issue. Do you have any other SPI slaves to try with?&lt;BR /&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
    <pubDate>Thu, 05 Jan 2023 21:24:57 GMT</pubDate>
    <dc:creator>AldoG</dc:creator>
    <dc:date>2023-01-05T21:24:57Z</dc:date>
    <item>
      <title>I.MX8MN Cortex M7 SPI problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX8MN-Cortex-M7-SPI-problem/m-p/1577001#M199485</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I'm trying to control a SPI slave with the cortex m7 of the IMX8M Nano, but i can't get correct data from slave.&lt;BR /&gt;when i monitor MISO pin without slave connected&amp;nbsp; i see some signals and if i connect the MISO pin of&amp;nbsp; the slave the signal is under 1V.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;SPI init:&lt;/P&gt;&lt;LI-CODE lang="cpp"&gt;ECSPI_MasterGetDefaultConfig(&amp;amp;masterConfig);
    masterConfig.baudRate_Bps = TRANSFER_BAUDRATE;
    masterConfig.rxFifoThreshold = 1;
    masterConfig.channelConfig.phase = kECSPI_ClockPhaseSecondEdge;
    masterConfig.channelConfig.channelMode = kECSPI_Master;

    ECSPI_MasterInit(ECSPI_MASTER_BASEADDR, &amp;amp;masterConfig, ECSPI_MASTER_CLK_FREQ);&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Pin_mux:&lt;/P&gt;&lt;LI-CODE lang="cpp"&gt;    IOMUXC_SetPinMux(IOMUXC_ECSPI1_MISO_ECSPI1_MISO, 0U);
    IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MISO_ECSPI1_MISO,
                        IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
    IOMUXC_SetPinMux(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI, 0U);
    IOMUXC_SetPinConfig(IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI,
                        IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
    IOMUXC_SetPinMux(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK, 0U);
    IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK,
                        IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
                        IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
    IOMUXC_SetPinMux(IOMUXC_ECSPI1_SS0_ECSPI1_SS0, 0U);
    IOMUXC_SetPinConfig(IOMUXC_ECSPI1_SS0_ECSPI1_SS0,
                        IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
                        IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
                        IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
    IOMUXC_SetPinMux(IOMUXC_UART3_RXD_UART3_RX, 0U);
    IOMUXC_SetPinConfig(IOMUXC_UART3_RXD_UART3_RX,
                        IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
                        IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));
    IOMUXC_SetPinMux(IOMUXC_UART3_TXD_UART3_TX, 0U);
    IOMUXC_SetPinConfig(IOMUXC_UART3_TXD_UART3_TX,
                        IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
                        IOMUXC_SW_PAD_CTL_PAD_FSEL(2U));&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;SPI transfer:&lt;/P&gt;&lt;LI-CODE lang="cpp"&gt;    ecspi_transfer_t masterXfer;
    masterXfer.txData   = txd;
    masterXfer.rxData   = rxd;
    masterXfer.dataSize = 6;
    masterXfer.channel  = kECSPI_Channel0;

    status_t error = ECSPI_MasterTransferBlocking(master_base_addr, &amp;amp;masterXfer);&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks&lt;BR /&gt;&lt;BR /&gt;Regards&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Joffrey&lt;/P&gt;</description>
      <pubDate>Wed, 04 Jan 2023 09:17:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX8MN-Cortex-M7-SPI-problem/m-p/1577001#M199485</guid>
      <dc:creator>Joffrey</dc:creator>
      <dc:date>2023-01-04T09:17:37Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX8MN Cortex M7 SPI problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX8MN-Cortex-M7-SPI-problem/m-p/1578171#M199631</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Have you tried one of the ECSPI examples available in the i.MX SDK?&lt;BR /&gt;Also, from the description it seems that the slave is having some issue. Do you have any other SPI slaves to try with?&lt;BR /&gt;&lt;BR /&gt;Best regards,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Thu, 05 Jan 2023 21:24:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX8MN-Cortex-M7-SPI-problem/m-p/1578171#M199631</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2023-01-05T21:24:57Z</dc:date>
    </item>
    <item>
      <title>Re: I.MX8MN Cortex M7 SPI problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MX8MN-Cortex-M7-SPI-problem/m-p/1578355#M199647</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Yes i have tried the examples.&lt;BR /&gt;&lt;BR /&gt;I have found 2 problems:&lt;/P&gt;&lt;P&gt;IN the imx8m nano from variscite, some slave are integrated to the som, i have put all chip select from other device (like touch screen and can) to VCC.&lt;BR /&gt;And when i put the chip select directly to the ground the communication is ok but when i use the chip select pin the slave doesn't work -&amp;gt; bad ground with prototype cable, after replacement of ground connection the transmission work.&lt;BR /&gt;&lt;BR /&gt;Thanks&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Joffrey.&lt;/P&gt;</description>
      <pubDate>Fri, 06 Jan 2023 06:19:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MX8MN-Cortex-M7-SPI-problem/m-p/1578355#M199647</guid>
      <dc:creator>Joffrey</dc:creator>
      <dc:date>2023-01-06T06:19:27Z</dc:date>
    </item>
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