<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Watchdog freeRTOS in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1577126#M199511</link>
    <description>&lt;P&gt;&lt;SPAN class="im"&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/183473"&gt;@Guy_L&lt;/a&gt;&amp;nbsp;,&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;Not all watchdogs can be used for reset of the system.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;In the I.MX8MM processor&amp;nbsp;&lt;STRONG&gt;WDOG3&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;is used for resetting the system (by asserting WDOG_RESET_B_DEB to SRC ).&lt;/DIV&gt;
&lt;DIV&gt;One can look at section&lt;STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;6.5.5.4 M4 Reset Control Register (SRC_M4RCR)&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in i.MX 8M Mini Applications Processor Reference Manual.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Bit [4:9] of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;SRC_M4RCR&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;determines the behavior of RESET in the M4 core.&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;SRC registers are defined as struct&amp;nbsp;&lt;STRONG&gt;SRC_Type&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in SDK_2_12_1_EVK-MIMX8MM/&lt;WBR /&gt;devices/MIMX8MM6/MIMX8MM6_cm4.&lt;WBR /&gt;h&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;For more information about system reset using watchdog one can refer to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;6.5 System Reset Controller (SRC)&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&lt;STRONG&gt;&amp;nbsp; 6.6.2.6.1 Watchdog reset generation&amp;nbsp;&lt;/STRONG&gt;in i.MX 8M Mini Applications Processor Reference Manual.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards,&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;</description>
    <pubDate>Wed, 04 Jan 2023 12:54:52 GMT</pubDate>
    <dc:creator>Sanket_Parekh</dc:creator>
    <dc:date>2023-01-04T12:54:52Z</dc:date>
    <item>
      <title>Watchdog freeRTOS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1574899#M199244</link>
      <description>&lt;P&gt;Hi NXP team,&lt;/P&gt;&lt;P&gt;I'm trying to figure out how to work with the fsl_wdog (version (2,1,1)).&lt;/P&gt;&lt;P&gt;If I'm initializing the watchdog (WDOG_Init) and never calling to&amp;nbsp;WDOG_Refresh the system resets after the timeout.&lt;/P&gt;&lt;P&gt;The problem is when I call to&amp;nbsp;WDOG_Refresh even once and then never calling it again, the system reset never happens.&lt;/P&gt;&lt;P&gt;Can you please advise?&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;P&gt;Guy&lt;/P&gt;</description>
      <pubDate>Tue, 27 Dec 2022 10:58:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1574899#M199244</guid>
      <dc:creator>Guy_L</dc:creator>
      <dc:date>2022-12-27T10:58:56Z</dc:date>
    </item>
    <item>
      <title>Re: Watchdog freeRTOS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1574963#M199253</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/183473"&gt;@Guy_L&lt;/a&gt;&amp;nbsp;,&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;I hope you are doing well.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;One can refer to&lt;STRONG&gt;&amp;nbsp;boards/evkmimx8mn/driver_&lt;WBR /&gt;examples/wdog/wdog.c and readme.txt&lt;/STRONG&gt;.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Please try with&amp;nbsp;the above example code by setting EXAMPLE_DISABLE_WDOG_RESET_&lt;WBR /&gt;FUNCTION to 0 and correct&amp;nbsp;DEMO_WDOG_BASE.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Please provide me with the Processor part number and Wdog information for further debugging.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;</description>
      <pubDate>Tue, 27 Dec 2022 16:07:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1574963#M199253</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2022-12-27T16:07:52Z</dc:date>
    </item>
    <item>
      <title>Re: Watchdog freeRTOS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1575916#M199361</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN&gt;Sanket&amp;nbsp; and thanks for your answer!&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;I've tried to write (0) to&amp;nbsp;EXAMPLE_DISABLE_WDOG_RESET_FUNCTION&amp;nbsp;but it didn't help.&lt;BR /&gt;The output I see is:&lt;/P&gt;&lt;P&gt;System reset by: Software Reset!&lt;/P&gt;&lt;P&gt;- 2.Testing system reset by WDOG timeout.&lt;BR /&gt;--- wdog Init done---&lt;/P&gt;&lt;P&gt;and the system just get "stuck" (the while (1) {} part) but but the reset never occurs.&lt;/P&gt;&lt;P&gt;The&amp;nbsp;DEMO_WDOG_BASE is set to&amp;nbsp;WDOG1.&lt;/P&gt;&lt;P&gt;The processor that I'm using is Cortex-M4 on&amp;nbsp;SOM dart mx8m mini&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you!&lt;/P&gt;</description>
      <pubDate>Sun, 01 Jan 2023 14:12:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1575916#M199361</guid>
      <dc:creator>Guy_L</dc:creator>
      <dc:date>2023-01-01T14:12:43Z</dc:date>
    </item>
    <item>
      <title>Re: Watchdog freeRTOS</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1577126#M199511</link>
      <description>&lt;P&gt;&lt;SPAN class="im"&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/183473"&gt;@Guy_L&lt;/a&gt;&amp;nbsp;,&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;Not all watchdogs can be used for reset of the system.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;In the I.MX8MM processor&amp;nbsp;&lt;STRONG&gt;WDOG3&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;is used for resetting the system (by asserting WDOG_RESET_B_DEB to SRC ).&lt;/DIV&gt;
&lt;DIV&gt;One can look at section&lt;STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;6.5.5.4 M4 Reset Control Register (SRC_M4RCR)&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in i.MX 8M Mini Applications Processor Reference Manual.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Bit [4:9] of&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;SRC_M4RCR&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;determines the behavior of RESET in the M4 core.&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;SRC registers are defined as struct&amp;nbsp;&lt;STRONG&gt;SRC_Type&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in SDK_2_12_1_EVK-MIMX8MM/&lt;WBR /&gt;devices/MIMX8MM6/MIMX8MM6_cm4.&lt;WBR /&gt;h&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;For more information about system reset using watchdog one can refer to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;6.5 System Reset Controller (SRC)&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&lt;STRONG&gt;&amp;nbsp; 6.6.2.6.1 Watchdog reset generation&amp;nbsp;&lt;/STRONG&gt;in i.MX 8M Mini Applications Processor Reference Manual.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards,&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 04 Jan 2023 12:54:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Watchdog-freeRTOS/m-p/1577126#M199511</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-01-04T12:54:52Z</dc:date>
    </item>
  </channel>
</rss>

