<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX Processors中的主题 Simple question regarding memory access</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1575898#M199360</link>
    <description>&lt;P&gt;Good day team,&lt;/P&gt;&lt;P&gt;I work on a NXP iMX RT1020-EVK board, ethernet module, and having code unable to fetch the ENET registers (polling others ok), see below traces (C and assembly source).&lt;/P&gt;&lt;P&gt;Could you please point out the required configuration to enable ENET module ?&lt;/P&gt;&lt;P&gt;I believe there is a peripheral or clock configuration to be done, though i can't find it in the man pages.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV class=""&gt;C source trace:&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;BLOCKQUOTE&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;PRINTF("Tests: begining\n\r");&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;uint32_t test_rdar_read_2;&lt;/DIV&gt;&lt;DIV class=""&gt;test_rdar_read_2 = ETH_test-&amp;gt;RDAR; // &amp;lt;&amp;lt;&amp;lt; Waits single step from here&lt;/DIV&gt;&lt;DIV class=""&gt;PRINTF("Tests: done. Reading ETH_test-&amp;gt;RDAR: %x \n\r", test_rdar_read_2);&lt;/DIV&gt;&lt;P&gt;PRINTF("Init done, MG strating ... \n\r");&lt;/P&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV class=""&gt;Assembly trace:&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;BLOCKQUOTE&gt;&lt;DIV class=""&gt;418 PRINTF("Tests: begining\n\r");&lt;/DIV&gt;&lt;DIV class=""&gt;20001756: ldr r0, [pc, #376] ; (0x200018d0 &amp;lt;main+404&amp;gt;)&lt;/DIV&gt;&lt;DIV class=""&gt;20001758: bl 0x2000664a &amp;lt;DbgConsole_Printf&amp;gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;421 test_rdar_read_2 = ETH_test-&amp;gt;RDAR&lt;/DIV&gt;&lt;DIV class=""&gt;2000175c: ldr r3, [pc, #372] ; (0x200018d4 &amp;lt;main+408&amp;gt;) &amp;lt;&amp;lt;&amp;lt; Waits single stop from here&lt;/DIV&gt;&lt;DIV class=""&gt;2000175e: ldr r3, [r3, #16]&lt;/DIV&gt;&lt;DIV class=""&gt;20001760: str.w r3, [r7, #240] ; 0xf0&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;P&gt;422 PRINTF("Tests: done. Reading ETH_test-&amp;gt;RDAR: %x \n\r", test_rdar_read_2);&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;P&gt;Jean-François&lt;/P&gt;</description>
    <pubDate>Sat, 31 Dec 2022 12:48:20 GMT</pubDate>
    <dc:creator>jfsimon1981</dc:creator>
    <dc:date>2022-12-31T12:48:20Z</dc:date>
    <item>
      <title>Simple question regarding memory access</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1575898#M199360</link>
      <description>&lt;P&gt;Good day team,&lt;/P&gt;&lt;P&gt;I work on a NXP iMX RT1020-EVK board, ethernet module, and having code unable to fetch the ENET registers (polling others ok), see below traces (C and assembly source).&lt;/P&gt;&lt;P&gt;Could you please point out the required configuration to enable ENET module ?&lt;/P&gt;&lt;P&gt;I believe there is a peripheral or clock configuration to be done, though i can't find it in the man pages.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;DIV class=""&gt;C source trace:&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;BLOCKQUOTE&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;PRINTF("Tests: begining\n\r");&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;uint32_t test_rdar_read_2;&lt;/DIV&gt;&lt;DIV class=""&gt;test_rdar_read_2 = ETH_test-&amp;gt;RDAR; // &amp;lt;&amp;lt;&amp;lt; Waits single step from here&lt;/DIV&gt;&lt;DIV class=""&gt;PRINTF("Tests: done. Reading ETH_test-&amp;gt;RDAR: %x \n\r", test_rdar_read_2);&lt;/DIV&gt;&lt;P&gt;PRINTF("Init done, MG strating ... \n\r");&lt;/P&gt;&lt;/DIV&gt;&lt;/BLOCKQUOTE&gt;&lt;DIV class=""&gt;Assembly trace:&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;BLOCKQUOTE&gt;&lt;DIV class=""&gt;418 PRINTF("Tests: begining\n\r");&lt;/DIV&gt;&lt;DIV class=""&gt;20001756: ldr r0, [pc, #376] ; (0x200018d0 &amp;lt;main+404&amp;gt;)&lt;/DIV&gt;&lt;DIV class=""&gt;20001758: bl 0x2000664a &amp;lt;DbgConsole_Printf&amp;gt;&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV class=""&gt;421 test_rdar_read_2 = ETH_test-&amp;gt;RDAR&lt;/DIV&gt;&lt;DIV class=""&gt;2000175c: ldr r3, [pc, #372] ; (0x200018d4 &amp;lt;main+408&amp;gt;) &amp;lt;&amp;lt;&amp;lt; Waits single stop from here&lt;/DIV&gt;&lt;DIV class=""&gt;2000175e: ldr r3, [r3, #16]&lt;/DIV&gt;&lt;DIV class=""&gt;20001760: str.w r3, [r7, #240] ; 0xf0&lt;/DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;P&gt;422 PRINTF("Tests: done. Reading ETH_test-&amp;gt;RDAR: %x \n\r", test_rdar_read_2);&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Thank you&lt;/P&gt;&lt;P&gt;Jean-François&lt;/P&gt;</description>
      <pubDate>Sat, 31 Dec 2022 12:48:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1575898#M199360</guid>
      <dc:creator>jfsimon1981</dc:creator>
      <dc:date>2022-12-31T12:48:20Z</dc:date>
    </item>
    <item>
      <title>Re: Simple question regarding memory access</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1576330#M199400</link>
      <description>&lt;P&gt;hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/209989"&gt;@jfsimon1981&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;You are correct, before reading ENET registers you need to do proper intialization.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;As an example, if you take a look at our RT1020 SDK examples, you will be able to see that ENET-&amp;gt;RDAR register can be read after calling the&amp;nbsp;PHY_Init() function. Below an snapshot.&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="diego_charles_0-1672725601638.png" style="width: 570px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/205916iA96BB71B70DFBF91/image-dimensions/570x215?v=v2" width="570" height="215" role="button" title="diego_charles_0-1672725601638.png" alt="diego_charles_0-1672725601638.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Best regards,&lt;/P&gt;
&lt;P&gt;Diego&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 03 Jan 2023 16:26:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Simple-question-regarding-memory-access/m-p/1576330#M199400</guid>
      <dc:creator>diego_charles</dc:creator>
      <dc:date>2023-01-03T16:26:38Z</dc:date>
    </item>
  </channel>
</rss>

