topic Re: Imx8 quad with Flash Memory Toggle in i.MX Processors

Imx8 quad with Flash Memory Toggle

shai_b — Sun, 06 Nov 2022 10:39:00 GMT

Dear Team,

My customer has a design with Imx8 quad and he has an inquiry about Flash Memory Toggle.

Could you please help me to understand the connection between the IMX8 quad(page 58) and the Flash DDR?

The customer don't know How to connect the below pin:

nDQS to Flash DDR
nRB[0..3]

Waiting for your kind feedback, Many thanks.

Best regards

Shai

Re: Imx8 quad with Flash Memory Toggle

shai_b — Wed, 14 Dec 2022 09:30:51 GMT

Dear team,

Could you please check my connection between the IMX8 quad and the toggle flash DDR, Attached schematics below:

I am not sure about the connections between NAND_nREADY and RE0, please review and advise back.

Waiting for your mind feedback, many thanks.

Kind regards,

Shai

Re: Imx8 quad with Flash Memory Toggle

brian14 — Mon, 19 Dec 2022 05:56:16 GMT

Hi, @shai_b

This type of NAND Flash Memory Toggle (ONFI NV-DDR2) based on iMX8 Quad datasheet is supported but I can't see the function of

RE0
NRE0
RNB0
ODT0

Could you please provide memory datasheet?

With this datasheet we will be able to resolve the function of this pins and identify the correct connection with the iMX8.

Best regards,
Brian.

Re: Imx8 quad with Flash Memory Toggle

shai_b — Sun, 25 Dec 2022 10:36:39 GMT

@brian14 Hello,

Please find attached the customer DDR datasheet, we waiting for your kind feedback.

Thanks a lot.

regards,

Shai

Re: Imx8 quad with Flash Memory Toggle

brian14 — Wed, 28 Dec 2022 22:24:27 GMT

Hi, Shai

Thank you for the datasheet.

Based on the provided datasheet RE0 and NRE0 are read-enable pins in differential signaling.
The i.MX NAND interface doesn't have support for a read enable working in differential signaling, but it seems that memory can work for some operations using only NRE0, so I can suggest testing operations using only this pin (as you connect) or changing the memory with a read enable with single-ended support.

About NAND_nREADY is right connected to RNB0 (Ready/Busy), but based on the provided schematic it seems that RNB0 is an input but the datasheet describes the Ready/Busy pin as an output.

In general, the pins are right connected but you have to test as a single-ended read enable pin and review the ready/busy pin as an output.

If you have any questions or concerns, don’t hesitate to let me know.

Best regards,
Brian.

Re: Imx8 quad with Flash Memory Toggle

shai_b — Tue, 10 Jan 2023 16:48:34 GMT

@brain
Thanks a lot for your support.
I will keep you posted as needed.

Kind regards,
Shai