topic Re: iMX6 SPI SS difference in i.MX Processors

iMX6 SPI SS difference

cliverolston — Wed, 26 Jun 2013 12:30:28 GMT

We have 2 ECSPI interfaces configured on our iMX6 quad core SPI2 and SPI3. We want to read 96 bytes in on the MISO line. This works fine on SPI2 - the SS stays low for the duration of the read. On SPI3 SS goes high between each byte. Our SPI drivers are identical, as far as we can tell. Is there any difference between the SPI interfaces on the chip?

Re: iMX6 SPI SS difference

RobinGong — Wed, 03 Jul 2013 04:48:19 GMT

Please take care of that SS pin should be configured GPIO output(arch/arm/mach-mx6/board-mx6q_sabresd.h). And should tell the GPIO number to SPI driver in board file , such as below code in arch/arm/mach-mx6/board-mx6q_sabresd.c

static int mx6q_sabresd_spi_cs[] = {

SABRESD_ECSPI1_CS0,

};

static const struct spi_imx_master mx6q_sabresd_spi_data __initconst = {

.chipselect = mx6q_sabresd_spi_cs,

.num_chipselect = ARRAY_SIZE(mx6q_sabresd_spi_cs),

};

Re: iMX6 SPI SS difference

cliverolston — Wed, 03 Jul 2013 08:20:35 GMT

Thanks Yibin,

We've tried this already but we're still having problems with SPI3.

Cheers,

Clive

Re: iMX6 SPI SS difference

RobinGong — Wed, 03 Jul 2013 08:31:17 GMT

Can you share the IOMUX setting about pins of SPI3? Such as:

/* ECSPI1 */

MX6Q_PAD_KEY_COL0__ECSPI1_SCLK,

MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI,

MX6Q_PAD_KEY_COL1__ECSPI1_MISO,

MX6Q_PAD_KEY_ROW1__GPIO_4_9,