i.MX 8M Mini USB in Linux 5.10.83

Arching — Wed, 16 Nov 2022 06:41:12 GMT

Hello!

We are developing a system based on Forlinx FETMX8MM_C SoM (i.MX 8M Mini): https://www.forlinx.net/product/imx8mm-system-on-module-28.html

The SoM vendor supplied us with a binary build of Linux 4.14.78-based OS which is too old for us. We use Buildroot 2021.02-based one based on Linux 5.10.83.

We've ported U-Boot and base OS but got stuck with USB support.

This is original device tree from board:

/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

/dts-v1/;

#include "fsl-imx8mm.dtsi"

/ {
model = "Forlinx i.MX8MM EVK board";
compatible = "forlinx,imx8mm-evk", "fsl,imx8mm";
clocks {
mcp251x_clock: mcp251x_clock{
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <8000000>;
};
};

chosen {
bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
stdout-path = &uart2;
};

leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;

status {
label = "status";
gpios = <&gpio3 16 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};

gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;

up {
label = "GPIO Key UP";
linux,code = <115>;
gpios = <&gpio4 31 GPIO_ACTIVE_LOW>;
};

down {
label = "GPIO Key DOWN";
linux,code = <114>;
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
};

home {
label = "GPIO Key HOME";
linux,code = <102>;
gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
};
};

modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
reset-post-delay-ms = <40>;
#reset-cells = <0>;
};

regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;

reg_sd1_vmmc: sd1_regulator {
compatible = "regulator-fixed";
regulator-name = "WLAN_EN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
off-on-delay = <20000>;
startup-delay-us = <100>;
enable-active-high;
};

reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
off-on-delay = <20000>;
enable-active-high;
};

reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

sound: sound {
compatible = "fsl,imx7d-evk-wm8960",
"fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai2>;
audio-codec = <&wm8960>;
codec-master;
hp-det-gpios = <&gpio4 22 0>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT2", "Mic Jack",
"RINPUT2", "Mic Jack",
"Mic Jack", "MICB",
"CPU-Playback", "ASRC-Playback",
"Playback", "CPU-Playback",
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
};
sound-micfil {
compatible = "fsl,imx-audio-micfil";
model = "imx-audio-micfil";
cpu-dai = <&micfil>;
};

backlight0: backlight@0 {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000 0>;

brightness-levels = < 0 23 23 23 23 23 23 23 23 23
23 23 23 23 23 23 23 23 23 23
23 23 23 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
};
};

&clk {
assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>;
assigned-clock-rates = <720000000>, <722534400>;
};

&iomuxc {
pinctrl-names = "default";

imx8mm-evk {
pinctrl_csi_pwn: csi_pwn_grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1
0x19
>;
};

pinctrl_csi_rst: csi_rst_grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0
0x19
MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
>;
};

pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9
0x19 /* Touch int */
>;
};

pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC
0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO
0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
0x1f
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10
0x19
>;
};

pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK
0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B
0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0
0x156
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1
0x156
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2
0x156
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3
0x156
>;
};

pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16
0x19
>;
};

pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL
0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA
0x400001c3
>;
};

pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL
0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA
0x400001c3
>;
};

pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL
0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA
0x400001c3
>;
};

pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL
0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA
0x400001c3
>;
};

pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5
0x41
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7
0x41
>;
};

pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3
0x41
>;
};

pinctrl_sai1: sai1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK
0xd6
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC
0xd6
MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC
0xd6
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK
0xd6
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0
0xd6
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1
0xd6
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
0xd6
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3
0xd6
MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4
0xd6
MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5
0xd6
MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6
0xd6
MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7
0xd6
>;
};

pinctrl_sai1_dsd: sai1grp_dsd {
fsl,pins = <
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK
0xd6
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC
0xd6
MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4
0xd6
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK
0xd6
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0
0xd6
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1
0xd6
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
0xd6
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3
0xd6
MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4
0xd6
MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5
0xd6
MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6
0xd6
MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7
0xd6
>;
};

pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
0xd6
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22
0xd6
>;
};

pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK
0xd6
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0
0xd6
MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1
0xd6
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2
0xd6
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3
0xd6
>;
};

pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX
0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX
0x140
>;
};

pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX
0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX
0x140
>;
};

pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX
0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX
0x140
>;
};

pinctrl_usdhc1_gpio: usdhc1grpgpio {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25
0x41
>;
};

pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
0x1d0
>;
};

pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
0x1d4
>;
};

pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK
0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD
0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0
0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1
0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2
0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3
0x1d6
>;
};

pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12
0x1c4
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19
0x41
>;
};

pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK
0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD
0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
0x1d0
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
0x1d0
>;
};

pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK
0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD
0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
0x1d4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
0x1d0
>;
};

pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK
0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD
0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0
0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1
0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2
0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3
0x1d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
0x1d0
>;
};

pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK
0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4
0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6
0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
0x190
>;
};

pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK
0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4
0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6
0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
0x194
>;
};

pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK
0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD
0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0
0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1
0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2
0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3
0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4
0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5
0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6
0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7
0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE
0x196
>;
};

pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
0xc6
>;
};

pinctrl_otg1_vbus_ctrl: otg1_vbus_ctrl {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19
0x100 //pull down
>;
};
pinctrl_otg2_vbus_ctrl: otg2_vbus_ctrl {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO05
0x100 //pull down
>;
};

pinctrl_gpio_keys: gpio_keys {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31
0x19
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28
0x19
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2
0x19
>;
};

pinctrl_spi1: spi1 {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK
0x1d0
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI
0x1d0
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO
0x1d0
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9
0x1d0
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3
0x159
>;
};

pinctrl_spi2: spi2 {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
0x1d0
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
0x1d0
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
0x1d0
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13
0x1d0
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
0x159
>;
};

pinctrl_pwm1: pwm1 {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT
0x1d0
>;
};
pinctrl_pwm2: pwm2 {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT
0x1d0
>;
};

pinctrl_pwm3: pwm3 {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT
0x1d0
>;
};

pinctrl_pwm4: pwm4 {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT
0x1d0
>;
};
pinctrl_ft5x06_int: ft5x06_int {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10
0x159
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9
0x159
>;
};

pinctrl_wm8960_power_en: wm8960_pw_en {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21
0x159
>;
};
};
};

&csi1_bridge {
fsl,mipi-mode;
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&csi1_mipi_ep>;
};
};
};

&flexspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
assigned-clocks = <&clk IMX8MM_CLK_QSPI_SRC>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;

flash0: mt25qu256aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "w25q128";
spi-max-frequency = <50000000>;
spi-nor,ddr-quad-read-dummy = <6>;
};
};

&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";

pmic: bd71837@4b {
reg = <0x4b>;
compatible = "rohm,bd71840", "rohm,bd71837";
/* PMIC BD71837 PMIC_nINT GPIO1_IO3 */
pinctrl-0 = <&pinctrl_pmic>;
gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;

gpo {
rohm,drv = <0x0C>;
/* 0b0000_1100 all gpos with cmos output mode */
};

regulators {
#address-cells = <1>;
#size-cells = <0>;

bd71837,pmic-buck2-uses-i2c-dvs;
bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */

buck1_reg: regulator@0 {
reg = <0>;
regulator-compatible = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};

buck2_reg: regulator@1 {
reg = <1>;
regulator-compatible = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};

buck3_reg: regulator@2 {
reg = <2>;
regulator-compatible = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
};

buck4_reg: regulator@3 {
reg = <3>;
regulator-compatible = "buck4";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
};

buck5_reg: regulator@4 {
reg = <4>;
regulator-compatible = "buck5";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};

buck6_reg: regulator@5 {
reg = <5>;
regulator-compatible = "buck6";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};

buck7_reg: regulator@6 {
reg = <6>;
regulator-compatible = "buck7";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};

buck8_reg: regulator@7 {
reg = <7>;
regulator-compatible = "buck8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};

ldo1_reg: regulator@8 {
reg = <8>;
regulator-compatible = "ldo1";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};

ldo2_reg: regulator@9 {
reg = <9>;
regulator-compatible = "ldo2";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};

ldo3_reg: regulator@10 {
reg = <10>;
regulator-compatible = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};

ldo4_reg: regulator@11 {
reg = <11>;
regulator-compatible = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};

ldo6_reg: regulator@13 {
reg = <13>;
regulator-compatible = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};

&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";

rtc@32 {
compatible = "rx8010";
reg = <0x32>;
status = "okay";
};

rtc8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
status = "okay";
};

wm8960: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wm8960_power_en>;
wlf,shared-lrclk;
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
clock-names = "mclk";
};
};

&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi1_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi1_ep>;
data-lanes = <2>;
csis-hs-settle = <13>;
csis-clk-settle = <2>;
csis-wclk;
};

csi1_mipi_ep: endpoint2 {
remote-endpoint = <&csi1_ep>;
};
};
};

&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";

};

&i2c4{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";

ft5x06_ts@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "defaults";
pinctrl-0 = <&pinctrl_ft5x06_int>;
interrupt-parent = <&gpio1>;
interrupts = <10 2>;
status = "okay";
};

gt928_ts@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ft5x06_int>;
interrupt-parent = <&gpio1>;
interrupts = <10 2>;
goodix,rst-gpio = <&gpio1 9 0>;
goodix,irq-gpio = <&gpio1 10 0>;
status = "disabled";

};

ov5640_mipi: ov5640_mipi@3c {
compatible = "ovti,ov5640_mipi";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>;
clocks = <&clk IMX8MM_CLK_CLKO1_DIV>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MM_CLK_CLKO1_SRC>,
<&clk IMX8MM_CLK_CLKO1_DIV>;
assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
assigned-clock-rates = <0>, <24000000>;
csi_id = <0>;
pwn-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
rst-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
mclk = <24000000>;
mclk_source = <0>;
port {
ov5640_mipi1_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
};
};
};

lt8912_bridge_480p: lt8912_480p@48 {
compatible = "lontium,lt8912-480P";
reg = <0x48>;
status = "disabled";

port {
lt8912_from_dsim_480p: endpoint {
remote-endpoint = <&dsim_to_lt8912_480p>;
};
};
};

lt8912_bridge_720p: lt8912_720p@48 {
compatible = "lontium,lt8912-720P";
reg = <0x48>;
status = "disabled";

port {
lt8912_from_dsim_720p: endpoint {
remote-endpoint = <&dsim_to_lt8912_720p>;
};
};
};

lt8912_bridge_1080p: lt8912_1080p@48 {
compatible = "lontium,lt8912-1080P";
reg = <0x48>;
status = "disabled";

port {
lt8912_from_dsim_1080p: endpoint {
remote-endpoint = <&dsim_to_lt8912_1080p>;
};
};
};

lt8912_bridge_WXGA: lt8912_wxga@48 {
compatible = "lontium,lt8912-WXGA";
reg = <0x48>;
status = "disabled";

port {
lt8912_from_dsim_wxga: endpoint {
remote-endpoint = <&dsim_to_lt8912_wxga>;
};
};
};

lt8912_bridge_CUSTOM: lt8912_custom@48 {
compatible = "lontium,lt8912-CUSTOM";
reg = <0x48>;
status = "disabled";

port {
lt8912_from_dsim_custom: endpoint {
remote-endpoint = <&dsim_to_lt8912_custom>;
};
};
display-timings {
timing {
clock-frequency = <74250000>;
hactive = <1280>;
vactive = <720>;
hfront-porch = <220>;
hsync-len = <40>;
hback-porch = <110>;
vfront-porch = <20>;
vsync-len = <5>;
vback-porch = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};

&lcdif {
status = "okay";
};

&mipi_dsi {
status = "okay";

panel@0 {
status = "disabled";
compatible = "forlinx,mipi7";
reg = <0>;
};

port@1 {
dsim_to_lt8912_480p: endpoint {
remote-endpoint = <&lt8912_from_dsim_480p>;
};
};

port@2 {
dsim_to_lt8912_720p: endpoint {
remote-endpoint = <&lt8912_from_dsim_720p>;
};
};

port@3 {
dsim_to_lt8912_1080p: endpoint {
remote-endpoint = <&lt8912_from_dsim_1080p>;
};
};

port@4 {
dsim_to_lt8912_wxga: endpoint {
remote-endpoint = <&lt8912_from_dsim_wxga>;
};
};

port@5 {
dsim_to_lt8912_custom: endpoint {
remote-endpoint = <&lt8912_from_dsim_custom>;
};
};
};

&mu {
status = "okay";
};

&rpmsg{
/*
* 64K for one rpmsg instance:
* --0xb8000000~0xb800ffff: pingpong
*/
vdev-nums = <1>;
reg = <0x0 0xb8000000 0x0 0x10000>;
status = "okay";
};

&sai1 {
pinctrl-names = "default", "dsd";
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1_dsd>;
assigned-clocks = <&clk IMX8MM_CLK_SAI1_SRC>,
<&clk IMX8MM_CLK_SAI1_DIV>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <49152000>;
clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
<&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
fsl,sai-multi-lane;
fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>;
dmas = <&sdma2 0 26 0>, <&sdma2 1 26 0>;
status = "disabled";
};

&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clk IMX8MM_CLK_SAI2_SRC>,
<&clk IMX8MM_CLK_SAI2_DIV>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <24000000>;
status = "okay";
};

&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";

mdio {
#address-cells = <1>;
#size-cells = <0>;

ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,led-act-blind-workaround;
at803x,eee-okay;
at803x,vddio-1p8v;
};
};
};

&pcie0{
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
disable-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
ext_osc = <1>;
status = "okay";
};

&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};

&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};

&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
};

&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};

&ecspi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
cs-gpios = <&gpio5 9 0>;

spidev@0 {
compatible = "spidev", "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <25000000>;
};
};

&ecspi2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 0>;

/*spidev@0 {
compatible = "spidev", "rohm,dh2228fv";
reg = <0>;
spi-max-frequency = <25000000>;
};*/
can0: mcp2515@0 {
compatible = "microchip,mcp2515";
reg = <0>;
spi-max-frequency = <10000000>;
clocks = <&mcp251x_clock>;
interrupt-parent = <&gpio5>;
interrupts = <5 0x2>;
};
};

&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MM_CLK_UART1_SRC>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
status = "okay";
};

&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};

&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3_SRC>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
status = "okay";
};

&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_otg1_vbus_ctrl>;

dr_mode = "otg";
vbus-supply = <&reg_usb_otg1_vbus>;
picophy,pre-emp-curr-control = <3>;
picophy,dc-vol-level-adjust = <7>;
status = "okay";
};

&usbotg2 {
dr_mode = "host";
picophy,pre-emp-curr-control = <3>;
picophy,dc-vol-level-adjust = <7>;
status = "okay";
};

&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_sd1_vmmc>;
pm-ignore-notify;
keep-power-in-suspend;
non-removable;
status = "okay";
};

&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};

&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};

&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};

&A53_0 {
arm-supply = <&buck2_reg>;
};

&gpu {
status = "okay";
};

&vpu_g1 {
status = "okay";
};

&vpu_g2 {
status = "okay";
};

&vpu_h1 {
status = "okay";
};

&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MM_CLK_PDM_SRC>, <&clk IMX8MM_CLK_PDM_DIV>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <196608000>;
status = "okay";
};

&snvs {
status = "disabled";
};

Almost everything works except of USBOTG2 controller. Our hardware designers use USBOTG2 controller for console port, therefore it is necessary to make it work.

But the problem is that when I make &usbotg2 node status = "okay", OS hangs on boot while initializing USB2 root hub.

When usbotg2 is disabled (therefore usbotg1 is the only USB hub), boot log is:

[ 29.122648] devices_kset: Moving 32e40000.usb to end of list
[ 29.128315] PM: Moving platform:32e40000.usb to end of list
[ 29.133895] platform 32e40000.usb: Retrying from deferred list
[ 29.140811] bus: 'platform': driver_probe_device: matched device 32e40000.usb with driver imx_usb
[ 29.149697] bus: 'platform': really_probe: probing driver imx_usb with device 32e40000.usb
[ 29.158039] imx_usb 32e40000.usb: no init pinctrl state
[ 29.163278] imx_usb 32e40000.usb: no sleep pinctrl state
[ 29.168599] imx_usb 32e40000.usb: no idle pinctrl state
[ 29.173912] imx_usb 32e40000.usb: No over current polarity defined
[ 29.180198] device: 'regulator:regulator.3--platform:32e40000.usb': device_add
[ 29.187487] devices_kset: Moving 32e40000.usb to end of list
[ 29.193164] PM: Moving platform:32e40000.usb to end of list
[ 29.198754] imx_usb 32e40000.usb: Linked as a consumer to regulator.3
[ 29.205229] Registering platform device 'ci_hdrc.0'. Parent at 32e40000.usb
[ 29.212198] device: 'ci_hdrc.0': device_add
[ 29.216393] bus: 'platform': add device ci_hdrc.0
[ 29.221127] PM: Adding info for platform:ci_hdrc.0
[ 29.226276] bus: 'platform': driver_probe_device: matched device ci_hdrc.0 with driver ci_hdrc
[ 29.234899] bus: 'platform': really_probe: probing driver ci_hdrc with device ci_hdrc.0
[ 29.242929] ci_hdrc ci_hdrc.0: no default pinctrl state
[ 29.250736] ci_hdrc ci_hdrc.0: EHCI Host Controller
[ 29.255649] ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
[ 29.279078] ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
[ 29.284611] device: 'usb1': device_add
[ 29.288438] bus: 'usb': add device usb1
[ 29.292320] PM: Adding info for usb:usb1
[ 29.297030] bus: 'usb': driver_probe_device: matched device usb1 with driver usb
[ 29.304441] bus: 'usb': really_probe: probing driver usb with device usb1
[ 29.311276] device: '1-0:1.0': device_add
[ 29.315327] bus: 'usb': add device 1-0:1.0
[ 29.319438] PM: Adding info for usb:1-0:1.0
[ 29.323660] bus: 'usb': driver_probe_device: matched device 1-0:1.0 with driver hub
[ 29.331328] bus: 'usb': really_probe: probing driver hub with device 1-0:1.0
[ 29.338395] hub 1-0:1.0: USB hub found
[ 29.342179] hub 1-0:1.0: 1 port detected
[ 29.346140] device: 'usb1-port1': device_add
[ 29.350440] PM: Adding info for No Bus:usb1-port1
[ 29.355196] driver: 'hub': driver_bound: bound to device '1-0:1.0'
[ 29.361411] bus: 'usb': really_probe: bound device 1-0:1.0 to driver hub
[ 29.368122] probe of 1-0:1.0 returned 1 after 36795 usecs
[ 29.373533] device: 'ep_81': device_add
[ 29.377406] PM: Adding info for No Bus:ep_81
[ 29.381694] driver: 'usb': driver_bound: bound to device 'usb1'
[ 29.387650] bus: 'usb': really_probe: bound device usb1 to driver usb
[ 29.394098] probe of usb1 returned 1 after 89659 usecs
[ 29.399250] device: 'ep_00': device_add
[ 29.403125] PM: Adding info for No Bus:ep_00
[ 29.407809] driver: 'ci_hdrc': driver_bound: bound to device 'ci_hdrc.0'
[ 29.414531] bus: 'platform': really_probe: bound device ci_hdrc.0 to driver ci_hdrc
[ 29.422196] probe of ci_hdrc.0 returned 1 after 187297 usecs
[ 29.427912] driver: 'imx_usb': driver_bound: bound to device '32e40000.usb'
[ 29.434887] imx_usb 32e40000.usb: Dropping the link to 30380000.clock-controller
[ 29.442290] device: 'platform:30380000.clock-controller--platform:32e40000.usb': device_unregister
[ 29.451304] imx_usb 32e40000.usb: Dropping the link to 30330000.pinctrl
[ 29.457928] device: 'platform:30330000.pinctrl--platform:32e40000.usb': device_unregister
[ 29.466148] imx_usb 32e40000.usb: Dropping the link to regulators:regulator@0
[ 29.473293] device: 'platform:regulators:regulator@0--platform:32e40000.usb': device_unregister
[ 29.482052] bus: 'platform': really_probe: bound device 32e40000.usb to driver imx_usb
[ 29.489978] probe of 32e40000.usb returned 1 after 340281 usecs

When usbotg2 is enabled:

[ 0.908457] i2c i2c-0: IMX I2C adapter registered
[ 0.914844] i2c i2c-1: IMX I2C adapter registered
[ 0.920724] i2c i2c-2: IMX I2C adapter registered
[ 0.926876] i2c i2c-3: IMX I2C adapter registered
[ 0.937644] imx_usb 32e50000.usb: No over current polarity defined
[ 0.946941] ci_hdrc ci_hdrc.0: EHCI Host Controller
[ 0.951860] ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
[ 0.961579] mmc2: new DDR MMC card at address 0001
[ 0.967150] mmcblk2: mmc2:0001 DG4008 7.28 GiB
[ 0.971846] mmcblk2boot0: mmc2:0001 DG4008 partition 1 4.00 MiB
[ 0.974999] ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
[ 0.977938] mmcblk2boot1: mmc2:0001 DG4008 partition 2 4.00 MiB
[ 0.984248] hub 1-0:1.0: USB hub found
[ 0.989769] mmcblk2rpmb: mmc2:0001 DG4008 partition 3 4.00 MiB, chardev (236:0)
[ 0.992868] hub 1-0:1.0: 1 port detected

I tried vanilla Linux 5.10.83 and Codeaurora 5.10.83, and it hangs when usbotg2 is enabled.

I've found that somebody "fixed" this on Symphony SOM this way:

&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usb_otg2_vbus>;
srp-disable;
hnp-disable;
adp-disable;
disable-over-current;
/delete-property/ usb-role-switch;
/*
* FIXME: having USB2 enabled hangs the boot just after:
* [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller
* [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1
* [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00
* [ 1.977203] hub 1-0:1.0: USB hub found
* [ 1.980987] hub 1-0:1.0: 1 port detected
*/
status = "disabled";
};

That is just our case but we need to make it work and we cannot just disable it.

I've tried to debug it adding printk() through kernel ci-imx initialization sequence, but it did not help at all - it stalls at different (and moving) places, for example:

printk("111");
int i = 20;
printk("222");

I've pinpointed the place when it hangs, and when initializing usbotg1, there is 111 and 222 in logs, but when initializing usbotg2 - there is only 111, after which system hangs. It cannot hang on integer assignment, maybe it hangs somewhere else? But how to locate it?

I have a running stock ROM based on 4.14.78 where usbotg2 works and I can compare system behaviour but currently I have absolutely no idea on what causes hanging.

Can somebody point me right direction to troubleshoot this?

topic Re: i.MX 8M Mini USB in Linux 5.10.83 in i.MX Processors

i.MX 8M Mini USB in Linux 5.10.83

Re: i.MX 8M Mini USB in Linux 5.10.83

Re: i.MX 8M Mini USB in Linux 5.10.83