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    <title>i.MX ProcessorsのトピックRe: Setting LPSPI4 DMR0 / DMR1 registers...?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Setting-LPSPI4-DMR0-DMR1-registers/m-p/1552429#M197458</link>
    <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/149507"&gt;@np&lt;/a&gt;&amp;nbsp;，&lt;BR /&gt;Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.&lt;BR /&gt;It should configure the LPSPI clock and enable the lpspi4 clock prior to setting the LPSPI's registers.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jeremyzhou_0-1668146919778.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/199992i0FF2180A1F057EF5/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jeremyzhou_0-1668146919778.png" alt="jeremyzhou_0-1668146919778.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jeremyzhou_1-1668146928621.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/199993i8196AE6853A0A1CE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jeremyzhou_1-1668146928621.png" alt="jeremyzhou_1-1668146928621.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;TIC&lt;/P&gt;
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&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 11 Nov 2022 06:09:04 GMT</pubDate>
    <dc:creator>jeremyzhou</dc:creator>
    <dc:date>2022-11-11T06:09:04Z</dc:date>
    <item>
      <title>Setting LPSPI4 DMR0 / DMR1 registers...?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Setting-LPSPI4-DMR0-DMR1-registers/m-p/1551906#M197422</link>
      <description>&lt;P&gt;Hi everyone,&lt;/P&gt;&lt;P&gt;I'm trying to use LPSPI4's DMR0 / DMR1 data match registers as transient storage, but it seems as though I'm missing something really obvious. Here's my startup test code (note that this deliberately doesn't trigger software reset (CR bit 1), because I want to see if DMR0 persists over reboot):&lt;/P&gt;&lt;P&gt;#define MYSPI LPSPI4&lt;/P&gt;&lt;P&gt;MYSPI-&amp;gt;CR = 0x1 + 0x8; // enable module (but don't reset it!)&lt;BR /&gt;printf("DMR0 Persistence test: 0x%08x\r\n", (unsigned int)(MYSPI-&amp;gt;DMR0));&lt;BR /&gt;MYSPI-&amp;gt;DMR0 = 0x12345678;&lt;BR /&gt;printf("DMR0 Readback test: 0x%08x\r\n", (unsigned int)(MYSPI-&amp;gt;DMR0));&lt;/P&gt;&lt;P&gt;This is outputting:&lt;/P&gt;&lt;P&gt;DMR0 Persistence test: 0x00000000&lt;BR /&gt;DMR0 Readback test: 0x00000000&lt;/P&gt;&lt;P&gt;What have I got wrong here?&lt;/P&gt;&lt;P&gt;Thanks, Nick&lt;/P&gt;&lt;P&gt;cc: &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/56840"&gt;@jeremyzhou&lt;/a&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 10 Nov 2022 10:13:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Setting-LPSPI4-DMR0-DMR1-registers/m-p/1551906#M197422</guid>
      <dc:creator>np</dc:creator>
      <dc:date>2022-11-10T10:13:45Z</dc:date>
    </item>
    <item>
      <title>Re: Setting LPSPI4 DMR0 / DMR1 registers...?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Setting-LPSPI4-DMR0-DMR1-registers/m-p/1552429#M197458</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/149507"&gt;@np&lt;/a&gt;&amp;nbsp;，&lt;BR /&gt;Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.&lt;BR /&gt;It should configure the LPSPI clock and enable the lpspi4 clock prior to setting the LPSPI's registers.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jeremyzhou_0-1668146919778.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/199992i0FF2180A1F057EF5/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jeremyzhou_0-1668146919778.png" alt="jeremyzhou_0-1668146919778.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="jeremyzhou_1-1668146928621.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/199993i8196AE6853A0A1CE/image-size/medium?v=v2&amp;amp;px=400" role="button" title="jeremyzhou_1-1668146928621.png" alt="jeremyzhou_1-1668146928621.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;TIC&lt;/P&gt;
&lt;P&gt;-------------------------------------------------------------------------------&lt;BR /&gt;Note:&lt;BR /&gt;- If this post answers your question, please click the "Mark Correct" button. Thank you!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;- We are following threads for 7 weeks after the last post, later replies are ignored&lt;BR /&gt;Please open a new thread and refer to the closed one, if you have a related question at a later point in time.&lt;BR /&gt;-------------------------------------------------------------------------------&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 11 Nov 2022 06:09:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Setting-LPSPI4-DMR0-DMR1-registers/m-p/1552429#M197458</guid>
      <dc:creator>jeremyzhou</dc:creator>
      <dc:date>2022-11-11T06:09:04Z</dc:date>
    </item>
    <item>
      <title>Re: Setting LPSPI4 DMR0 / DMR1 registers...?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Setting-LPSPI4-DMR0-DMR1-registers/m-p/1555840#M197682</link>
      <description>&lt;P&gt;Worked perfectly, thanks Jeremy! &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 17 Nov 2022 13:37:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Setting-LPSPI4-DMR0-DMR1-registers/m-p/1555840#M197682</guid>
      <dc:creator>np</dc:creator>
      <dc:date>2022-11-17T13:37:28Z</dc:date>
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