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    <title>i.MX ProcessorsのトピックMCIMX8QXP-CPU</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1534929#M196167</link>
    <description>&lt;P&gt;Hello All,&lt;/P&gt;&lt;P&gt;I would like to know which class of PCB is the board of the MCIMX8QXP-CPU kit. I cannot find a table where I can make a direct&amp;nbsp; link between the minimum line width and the PCB class. I know that higher the class, thinner the lines. I saw that the majority of the lines on the PCB are 0.1mm width with some lines with 0.06mm widht. Can you help me?&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;/P&gt;&lt;P&gt;Nerea&lt;/P&gt;</description>
    <pubDate>Mon, 10 Oct 2022 13:57:47 GMT</pubDate>
    <dc:creator>NereaB</dc:creator>
    <dc:date>2022-10-10T13:57:47Z</dc:date>
    <item>
      <title>MCIMX8QXP-CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1534929#M196167</link>
      <description>&lt;P&gt;Hello All,&lt;/P&gt;&lt;P&gt;I would like to know which class of PCB is the board of the MCIMX8QXP-CPU kit. I cannot find a table where I can make a direct&amp;nbsp; link between the minimum line width and the PCB class. I know that higher the class, thinner the lines. I saw that the majority of the lines on the PCB are 0.1mm width with some lines with 0.06mm widht. Can you help me?&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;/P&gt;&lt;P&gt;Nerea&lt;/P&gt;</description>
      <pubDate>Mon, 10 Oct 2022 13:57:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1534929#M196167</guid>
      <dc:creator>NereaB</dc:creator>
      <dc:date>2022-10-10T13:57:47Z</dc:date>
    </item>
    <item>
      <title>Re: MCIMX8QXP-CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1537694#M196361</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/207236"&gt;@NereaB&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I hope you are doing well.&lt;BR /&gt;Please accept my apologies for the delay in response.&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;MCIMX8QXP-CPU MEK kit has been fabricated as per the PCB IPC class &lt;STRONG&gt;IPC-A-600&lt;/STRONG&gt;.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Ritesh M Patel&lt;/P&gt;</description>
      <pubDate>Fri, 14 Oct 2022 08:40:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1537694#M196361</guid>
      <dc:creator>riteshmpatel</dc:creator>
      <dc:date>2022-10-14T08:40:00Z</dc:date>
    </item>
    <item>
      <title>Re: MCIMX8QXP-CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1538664#M196451</link>
      <description>&lt;P&gt;Thanks! Do you know which is the minimum line width used in the design?&lt;/P&gt;&lt;P&gt;Thanks in advance,&lt;/P&gt;&lt;P&gt;Nerea&lt;/P&gt;</description>
      <pubDate>Mon, 17 Oct 2022 15:17:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1538664#M196451</guid>
      <dc:creator>NereaB</dc:creator>
      <dc:date>2022-10-17T15:17:29Z</dc:date>
    </item>
    <item>
      <title>Re: MCIMX8QXP-CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1540072#M196551</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/207236"&gt;@NereaB&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Kindly refer to the impedance table (Fab layer) in the EVK PCB layout.&lt;/P&gt;
&lt;P&gt;As per the Impedance table, the minimum trace width used is 3.5 mils for routing 100R differential signals.&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Ritesh M Patel&lt;/P&gt;</description>
      <pubDate>Wed, 19 Oct 2022 11:39:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1540072#M196551</guid>
      <dc:creator>riteshmpatel</dc:creator>
      <dc:date>2022-10-19T11:39:56Z</dc:date>
    </item>
    <item>
      <title>Re: MCIMX8QXP-CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1540093#M196557</link>
      <description>&lt;P&gt;Thanks &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/201596"&gt;@riteshmpatel&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;Is there any other trace which is smaller but it is not on the impedance table?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 19 Oct 2022 12:23:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1540093#M196557</guid>
      <dc:creator>NereaB</dc:creator>
      <dc:date>2022-10-19T12:23:39Z</dc:date>
    </item>
    <item>
      <title>Re: MCIMX8QXP-CPU</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1540119#M196564</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/207236"&gt;@NereaB&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Due to the design constraints, very few signals are routed with 2.5 mils in the layout and this is the minimum trace width used in the design.&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Ritesh M Patel&lt;/P&gt;</description>
      <pubDate>Wed, 19 Oct 2022 13:22:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MCIMX8QXP-CPU/m-p/1540119#M196564</guid>
      <dc:creator>riteshmpatel</dc:creator>
      <dc:date>2022-10-19T13:22:45Z</dc:date>
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