How to jtag imx93 - help

fatalfeel2 — Tue, 27 Sep 2022 18:34:42 GMT

1. Jtag Tap ID

2. Debug Base Address

3. cross trigger interface address

any idea for it?
(imx93 is armv8-a cortex-a55)

##this is from openocd renesas_rz_g2.cfg for cortex-a55
set CA55_DBGBASE {0x10E10000 0x10F10000}
set CA55_CTIBASE {0x10E20000 0x10F20000}

Re: How to jtag imx93 - help

fatalfeel2 — Sat, 01 Oct 2022 18:40:07 GMT

I add 2 explore file can auto display the debug base , cit , tap id
https://github.com/fatalfeel/openocd_integrated/tree/master/tcl/test

openocd -f /opt/openocd/share/openocd/scripts/test/explore_jtag.cfg
openocd -f /opt/openocd/share/openocd/scripts/test/explore_swd.cfg

now you can see all the info

example:
target stay on uboot console
u-boot=>

~~then
root@homelinux:~/openocd_swd# openocd -f /opt/openocd/share/openocd/scripts/test/explore_swd.cfg
Open On-Chip Debugger 0.12.0-rc1+dev
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : FTDI SWD mode enabled
Info : clock speed 1000 kHz
Info : SWD DPIDR 0x5ba02477
Error: [unknowCHIP.cpu.0] CTI not specified
Warn : target unknowCHIP.cpu.0 examination failed
Info : starting gdb server for unknowCHIP.cpu.0 on 3333
Info : Listening on port 3333 for gdb connections
Info : SWD DPIDR 0x5ba02477
AP # 0x1
AP ID register 0x44770002
Type is MEM-AP APB2 or APB3
MEM-AP BASE 0x80000000
ROM table in legacy format
Component base address 0x80000000
Peripheral ID 0x000008e88e
Designer is 0x00e, Freescale (Motorola)
Part is 0x88e, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory not present: dedicated debug bus
ROMTABLE[0x0] = 0x00400003
Component base address 0x80400000
Peripheral ID 0x04004bb4a1
Designer is 0x23b, ARM Ltd
Part is 0x4a1, Cortex-A53 ROM (v8 Memory Map ROM Table)
Component class is 0x1, ROM table
MEMTYPE system memory not present: dedicated debug bus
[L01] ROMTABLE[0x0] = 0x00010003
Component base address 0x80410000
Peripheral ID 0x04004bbd03
Designer is 0x23b, ARM Ltd
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
Dev Arch is 0x47706a15, ARM Ltd "Processor debug architecture (v8.0-A)" rev.0
[L01] ROMTABLE[0x4] = 0x00020003
Component base address 0x80420000
Peripheral ID 0x04004bb9a8
Designer is 0x23b, ARM Ltd
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
[L01] ROMTABLE[0x8] = 0x00030003
Component base address 0x80430000
Peripheral ID 0x04004bb9d3
Designer is 0x23b, ARM Ltd
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
[L01] ROMTABLE[0xc] = 0x00040003
Component base address 0x80440000
Peripheral ID 0x04004bb95d
Designer is 0x23b, ARM Ltd
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
Dev Arch is 0x47704a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.0
[L01] ROMTABLE[0x10] = 0x00110003
Component base address 0x80510000
Peripheral ID 0x04004bbd03
Designer is 0x23b, ARM Ltd
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
Dev Arch is 0x47706a15, ARM Ltd "Processor debug architecture (v8.0-A)" rev.0
[L01] ROMTABLE[0x14] = 0x00120003
Component base address 0x80520000
Peripheral ID 0x04004bb9a8
Designer is 0x23b, ARM Ltd
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
[L01] ROMTABLE[0x18] = 0x00130003
Component base address 0x80530000
Peripheral ID 0x04004bb9d3
Designer is 0x23b, ARM Ltd
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
[L01] ROMTABLE[0x1c] = 0x00140003
Component base address 0x80540000
Peripheral ID 0x04004bb95d
Designer is 0x23b, ARM Ltd
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
Dev Arch is 0x47704a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.0
[L01] ROMTABLE[0x20] = 0x00210003
Component base address 0x80610000
Peripheral ID 0x04004bbd03
Designer is 0x23b, ARM Ltd
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
Dev Arch is 0x47706a15, ARM Ltd "Processor debug architecture (v8.0-A)" rev.0
[L01] ROMTABLE[0x24] = 0x00220003
Component base address 0x80620000
Peripheral ID 0x04004bb9a8
Designer is 0x23b, ARM Ltd
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
[L01] ROMTABLE[0x28] = 0x00230003
Component base address 0x80630000
Peripheral ID 0x04004bb9d3
Designer is 0x23b, ARM Ltd
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
[L01] ROMTABLE[0x2c] = 0x00240003
Component base address 0x80640000
Peripheral ID 0x04004bb95d
Designer is 0x23b, ARM Ltd
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
Dev Arch is 0x47704a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.0
[L01] ROMTABLE[0x30] = 0x00310003
Component base address 0x80710000
Peripheral ID 0x04004bbd03
Designer is 0x23b, ARM Ltd
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
Dev Arch is 0x47706a15, ARM Ltd "Processor debug architecture (v8.0-A)" rev.0
[L01] ROMTABLE[0x34] = 0x00320003
Component base address 0x80720000
Peripheral ID 0x04004bb9a8
Designer is 0x23b, ARM Ltd
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
Dev Arch is 0x47701a14, ARM Ltd "Cross Trigger Interface (CTI) architecture" rev.0
[L01] ROMTABLE[0x38] = 0x00330003
Component base address 0x80730000
Peripheral ID 0x04004bb9d3
Designer is 0x23b, ARM Ltd
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
Dev Arch is 0x47702a16, ARM Ltd "Processor Performance Monitor (PMU) architecture" rev.0
[L01] ROMTABLE[0x3c] = 0x00340003
Component base address 0x80740000
Peripheral ID 0x04004bb95d
Designer is 0x23b, ARM Ltd
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
Dev Arch is 0x47704a13, ARM Ltd "Embedded Trace Macrocell (ETM) architecture" rev.0
[L01] ROMTABLE[0x40] = 0x00000000
[L01] End of ROM table
ROMTABLE[0x4] = 0x00800003
Component base address 0x80800000
Can't read component, the corresponding core might be turned off

Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections

Re: How to jtag imx93 - help

sinanakman — Thu, 06 Oct 2022 16:10:01 GMT

It looks like your ID is 0x5ba02477and for the first core debug address seems to be at 0x80420000 (you can probably ignore CTI now and try to debug one core first).

Hope this helps

Sinan Akman

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How to jtag imx93 - help

Re: How to jtag imx93 - help

Re: How to jtag imx93 - help