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    <title>topic Re: MIPI DSI with only ONE data lane on imx8qxp in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-DSI-with-only-ONE-data-lane-on-imx8qxp/m-p/1527909#M195599</link>
    <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&amp;nbsp; I have the same issue, but in my case I cannot see the signals switching to two data lanes. One data lane does not work because it is necessary to patch the file drivers/gpu/drm/bridge/nwl-dsi.c&lt;/P&gt;&lt;P&gt;&amp;nbsp; The function nwl_dsi_bridge_atomic_check makes lanes=1 not a choice&lt;/P&gt;&lt;P&gt;if (config-&amp;gt;lanes &amp;lt; 2 || config-&amp;gt;lanes &amp;gt; 4)&lt;BR /&gt;&amp;nbsp; return -EINVAL;&lt;/P&gt;&lt;P&gt;&amp;nbsp; With "(config-&amp;gt;lanes &amp;lt; 1" the function continues executing.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please let me know if it works for you&lt;/P&gt;</description>
    <pubDate>Mon, 26 Sep 2022 07:15:29 GMT</pubDate>
    <dc:creator>manuelcarrascos</dc:creator>
    <dc:date>2022-09-26T07:15:29Z</dc:date>
    <item>
      <title>MIPI DSI with only ONE data lane on imx8qxp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-DSI-with-only-ONE-data-lane-on-imx8qxp/m-p/1378204#M183656</link>
      <description>&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;We simply cannot make a small display (368x448, one DSI data lane only) work on a imx8qxp. No matter what timings we use for the display, there are no MIPI signals neither on the clock nor on MIPI_DSI0_DATA0_N/P. If we switch to two data lanes, we can see neat mipi signals. A dmesg | grep -n "drm" gives the following output:&lt;/P&gt;&lt;LI-SPOILER&gt;268:[ 2.107833] [drm] Initialized vivante 1.0.0 20170808 for 80000000.imx8_gpu0_ss on minor 0&lt;BR /&gt;329:[ 2.618298] nwl-dsi 56228000.dsi_host: [drm:nwl_dsi_host_attach] lanes=1, format=0x0 flags=0x805&lt;BR /&gt;330:[ 2.627235] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).&lt;BR /&gt;331:[ 2.633878] [drm] No driver support for vblank timestamp query.&lt;BR /&gt;332:[ 2.639883] imx-drm display-subsystem: bound imx-drm-dpu-bliteng.2 (ops 0xffff800010f8ca40)&lt;BR /&gt;333:[ 2.648899] imx-drm display-subsystem: bound imx-dpu-crtc.0 (ops 0xffff800010f8c710)&lt;BR /&gt;334:[ 2.657216] imx-drm display-subsystem: bound imx-dpu-crtc.1 (ops 0xffff800010f8c710)&lt;BR /&gt;335:[ 2.665384] imx-drm display-subsystem: bound 56228000.dsi_host (ops 0xffff800010f9e380)&lt;BR /&gt;336:[ 2.673927] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 1&lt;BR /&gt;339:[ 2.696574] imx-drm display-subsystem: fb0: imx-drmdrmfb frame buffer device&lt;BR /&gt;422:[ 4.760206] systemd[1]: Starting Load Kernel Module drm...&lt;/LI-SPOILER&gt;&lt;P&gt;It looks like everything is fine, but we noticed that the DSI driver is not calling the "prepare" nor the "enable" functions of the panel driver when dsi.lanes=1, hence the display is not initialised properly. It does call everyting correctly when dsi.lanes=2.&lt;/P&gt;&lt;P&gt;Has anyone else encountered a similar issue? Any idea what could be wrong?&lt;/P&gt;&lt;P&gt;Cheers,&lt;/P&gt;&lt;P&gt;Olli&lt;/P&gt;</description>
      <pubDate>Mon, 29 Nov 2021 12:42:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-DSI-with-only-ONE-data-lane-on-imx8qxp/m-p/1378204#M183656</guid>
      <dc:creator>olliistmeinname</dc:creator>
      <dc:date>2021-11-29T12:42:44Z</dc:date>
    </item>
    <item>
      <title>Re: MIPI DSI with only ONE data lane on imx8qxp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIPI-DSI-with-only-ONE-data-lane-on-imx8qxp/m-p/1527909#M195599</link>
      <description>&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&amp;nbsp; I have the same issue, but in my case I cannot see the signals switching to two data lanes. One data lane does not work because it is necessary to patch the file drivers/gpu/drm/bridge/nwl-dsi.c&lt;/P&gt;&lt;P&gt;&amp;nbsp; The function nwl_dsi_bridge_atomic_check makes lanes=1 not a choice&lt;/P&gt;&lt;P&gt;if (config-&amp;gt;lanes &amp;lt; 2 || config-&amp;gt;lanes &amp;gt; 4)&lt;BR /&gt;&amp;nbsp; return -EINVAL;&lt;/P&gt;&lt;P&gt;&amp;nbsp; With "(config-&amp;gt;lanes &amp;lt; 1" the function continues executing.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Please let me know if it works for you&lt;/P&gt;</description>
      <pubDate>Mon, 26 Sep 2022 07:15:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIPI-DSI-with-only-ONE-data-lane-on-imx8qxp/m-p/1527909#M195599</guid>
      <dc:creator>manuelcarrascos</dc:creator>
      <dc:date>2022-09-26T07:15:29Z</dc:date>
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