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    <title>topic LPSPI Clocking in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1521421#M195084</link>
    <description>&lt;P&gt;Why is it that whatever clock freq I configure the wire frequency I see is half that? I only ever see the CCR's PreScaler set to 0 as well.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;srcClock_Hz = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk) / (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); //80 mHz&lt;BR /&gt;LPSPI_MasterInit(LPSPI1, &amp;amp;masterConfig, srcClock_Hz);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Yet I see 40mHz on my scope.&lt;/P&gt;</description>
    <pubDate>Tue, 13 Sep 2022 19:52:16 GMT</pubDate>
    <dc:creator>mspenard603</dc:creator>
    <dc:date>2022-09-13T19:52:16Z</dc:date>
    <item>
      <title>LPSPI Clocking</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1521421#M195084</link>
      <description>&lt;P&gt;Why is it that whatever clock freq I configure the wire frequency I see is half that? I only ever see the CCR's PreScaler set to 0 as well.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;srcClock_Hz = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk) / (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U); //80 mHz&lt;BR /&gt;LPSPI_MasterInit(LPSPI1, &amp;amp;masterConfig, srcClock_Hz);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Yet I see 40mHz on my scope.&lt;/P&gt;</description>
      <pubDate>Tue, 13 Sep 2022 19:52:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1521421#M195084</guid>
      <dc:creator>mspenard603</dc:creator>
      <dc:date>2022-09-13T19:52:16Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Clocking</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1522857#M195198</link>
      <description>&lt;P&gt;srcClock_Hz is just LPSPI module functional clock, i believe what you mean is masterConfig.baudRate&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;#define TRANSFER_BAUDRATE 500000U /*! Transfer baudrate - 500k */

LPSPI_MasterGetDefaultConfig(&amp;amp;masterConfig);
masterConfig.baudRate = TRANSFER_BAUDRATE;
masterConfig.whichPcs = EXAMPLE_LPSPI_MASTER_PCS_FOR_INIT;

srcClock_Hz = (CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk) / (EXAMPLE_LPSPI_CLOCK_SOURCE_DIVIDER + 1U));
LPSPI_MasterInit(EXAMPLE_LPSPI_MASTER_BASEADDR, &amp;amp;masterConfig, srcClock_Hz);&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 15 Sep 2022 10:20:34 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1522857#M195198</guid>
      <dc:creator>jay_heng</dc:creator>
      <dc:date>2022-09-15T10:20:34Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Clocking</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1523045#M195227</link>
      <description>Well, my baud rate is: #define TRANSFER_BAUDRATE 100000000U&lt;BR /&gt;And my functional clock freq is 80mhz. So I'm wonder how and why it is that my line freq is 40mhz.</description>
      <pubDate>Thu, 15 Sep 2022 15:53:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1523045#M195227</guid>
      <dc:creator>mspenard603</dc:creator>
      <dc:date>2022-09-15T15:53:16Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Clocking</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1523227#M195238</link>
      <description>&lt;P&gt;You want to set TRANSFER_BAUDRATE to 100MHz, even greater than functional clock 80MHz? it should be invalid case, and there will be roll-back issue in LPSPI driver&lt;/P&gt;</description>
      <pubDate>Fri, 16 Sep 2022 00:28:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1523227#M195238</guid>
      <dc:creator>jay_heng</dc:creator>
      <dc:date>2022-09-16T00:28:25Z</dc:date>
    </item>
    <item>
      <title>Re: LPSPI Clocking</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1523615#M195263</link>
      <description>There is a 1 to 1 correspondence between TRANSFER_BAUDRATE and functional clock frequency?&lt;BR /&gt;&lt;BR /&gt;This is for a ATWINC1500 module. Their example code has a TRANSFER_BAUDRATE of 100000000U and a maximum SPI clock freq of 40mHz.</description>
      <pubDate>Fri, 16 Sep 2022 11:55:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPSPI-Clocking/m-p/1523615#M195263</guid>
      <dc:creator>mspenard603</dc:creator>
      <dc:date>2022-09-16T11:55:24Z</dc:date>
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