i.MX ProcessorsのトピックRe: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

jimmyli — Wed, 31 Aug 2022 03:43:53 GMT

Hi,

We selected i.MX6ULL(MCIMX6Y2CVM05AB) for our project, and runing the bare code provide by official SDK, rather than linux.

Now, we are going to use EIM interface to extand FPGA (our code is in nor flash through QSPI), but the SDK didn't provide the example about EIM. So, we config the EIM interface as to i.mx6ull reference manual. EIM interface can work, but some problems occur that we don't know why.

Below the problem that help you can provide some advices to help us.

1>test code,

see attachment《test-EIM》.

Note: Only select CS0_B / Data0-15 / RW external signals.

2>EIM logical wave.

see attachment 《test-Wave》.

3>problem

a. when CS is low, data lines can transfer right data.

b. when CS is high, data lines can't transfer right data;

c. Question: our design is that CS must hold low while transfering all 256 bytes data, but CS will turn high abnormally while transfering 256 bytes data.

How can we fix the problem, or another eim example code to help us ?

Thanks very much.

----EIM data wave

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

Sanket_Parekh — Wed, 07 Sep 2022 04:35:34 GMT

Hi @jimmyli

I hope you are doing well.

The reason behind CS pin is remains high is 100k Pull up is applied in firmware configuration. Please find the reference from below.

//EIM DATA0-15 CS RW
IOMUXC_SetPinMux(IOMUXC_CSI_MCLK _EIM_CS0_B, 0U);
IOMUXC_SetPinConfig(IOMUXC_CSI_MCLK_EIM_CS0_B,
IOMUXC_SW_PAD_CTL_PAD_DSE(2U) |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
IOMUXC_SW_PAD_CTL_PAD_PUS(2U));

PUS = 2 means 100K pull up from software. Please change the value of PUS to 0U, that means 100K pull down. After that CS pin remains low during the data transmission.

Thanks & Regards

Sanket Parekh

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

jimmyli — Wed, 07 Sep 2022 07:24:27 GMT

Hi Sanket,

It's very appriciated for your helpful reply.

I will try and test.

Thanks again.

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

Sanket_Parekh — Thu, 22 Sep 2022 11:58:41 GMT

Hi @jimmyli

I hope you are doing well.

can you please send the schematic of your board as we need to cross-check if any other module is not driving CS0 Pin?

Thanks & Regards

Sanket Parekh

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

Sanket_Parekh — Mon, 26 Sep 2022 07:23:44 GMT

Hi @jimmyli

Waiting for your response.

Thanks & Regards

Sanket Parekh

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

jimmyli — Wed, 28 Sep 2022 13:11:46 GMT

Hi Sanket,

I haven't customer's schematic yet, but below is the logical wave that can help you to understand.

Thanks.

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

Sanket_Parekh — Fri, 30 Sep 2022 12:49:36 GMT

Hi @jimmyli ,

I hope you are doing well.

As you are developing the test app to transfer 256 bytes of data through EIM, your configuration of WCR is not correct for the same.

you should keep the WWSC value as low as possible. To configure other bits of WCR for your need you can refer to section 21.9 in the RM.

Thanks & Regards

Sanket Parekh

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

jimmyli — Sat, 08 Oct 2022 08:56:22 GMT

Hi Sanket,

Sorry for replying too late.

I will try again and give you a feedback asap.

Thanks very much.

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

Sanket_Parekh — Wed, 12 Oct 2022 04:00:13 GMT

Hi @jimmyli

Waiting for your response.

Thanks & Regards

Sanket Parekh

Re: i.mx6ull extend to FPGA by EIM interface with bare code (or freertos)

jimmyli — Mon, 21 Nov 2022 23:48:01 GMT

Hi Sanket,

Sorry for replying too late.

We have tested the mathede that you applied, but it can't work well.

Do you have other tips to us ?

Thanks very much.