topic Re: IMXRT1064 Smart External Memory Pin Mux Overview in i.MX Processors

IMXRT1064 Smart External Memory Pin Mux Overview

Lukas_Frank — Fri, 26 Aug 2022 11:25:12 GMT

Hi Dear Authorized,

I have following questions related to Smart External Memory Controller.

Q1: Why don't we have BA0 and BA1 usage for SRAM as seen in below (SEMC_SRAM_Q1_Pic.png).

Q2: What 'ADV#', 'ALE' and 'DCX' means ? I can't find abbreviation for it.

Q3:What does Bank Address Bits (BA0 and BA1) exactly for SDRAM? Why SRAM/NAND/NOR/DBI does not have BA0 and BA1. I can't find exact definitions for BA.

Thanks and Regards.

Re: IMXRT1064 Smart External Memory Pin Mux Overview

Hui_Ma — Thu, 01 Sep 2022 13:23:05 GMT

Hi,

1. Merey range: Region #6 for SRAM device, which is for parallel SRAM device.
I just using a PSRAM chip Datasheet as an example.
2. ADV: Adress valid;

ALE: Address latch enable;

DCX: Using for DBI(Display Bus Interface), transmit Data/Command control;
3. Parallel SRAM does not have Bank concept, the chip select will control selected external memory device;

Thanks for the attention.

Mike

Re: IMXRT1064 Smart External Memory Pin Mux Overview

Lukas_Frank — Mon, 05 Sep 2022 10:18:38 GMT

Hi Dear @Hui_Ma ,

Thank you. I just want to clarify something. I wouldn't know meaning of ADV, ALE and DCX if you don't tell me. I searched them in Reference Manual but I can't find it. Is there a document that includes such kind of abbreviations?

Thanks and Regards.

Re: IMXRT1064 Smart External Memory Pin Mux Overview

Hui_Ma — Tue, 06 Sep 2022 02:26:56 GMT

Hi Lukas,

I am sorry our document missing related abbreviation description. In general, related signal description would be described at external memory chips' datasheet. Thanks.

Mike