topic Re: SDMA access from M4 core in i.MX Processors

SDMA access from M4 core

LennartB — Wed, 31 Aug 2022 07:01:38 GMT

I'm trying to initialize the SDMA from the M4 core of the i.MX8M. I followed the steps from the "i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference Manual", Rev. 3.1, 06/2021, pages 1101 - 1102. I configure channel 0 to copy the context data to ARM memory (i.e. channel 0 command "C0_GETCTXT"). Channel 0 seems to start and finishes as well (as indicated by STOP_STAT, contradictory with the reference manual, the SDMA_SDMA_INTR does not reflect this). However, no data seems to be written by the SDMA. I am using the TCM and even tried disabling the cache, but this doesn't influence the result.

Why is the context data not visible in ARM RAM?

Re: SDMA access from M4 core

ceggers — Wed, 31 Aug 2022 07:09:35 GMT

Hi Lennart,

at least the Linux driver doesn't use the interrupt for channel0, it uses busy-wait instead.

But there's nothing special about IRQs on channel0, if the IRQ bit in the mode field of the buffer descriptor is set, you should get an interrupt.

I have a JTAG debugger for the SDMA, it can help to debug such problems.

regards
Christian

Re: SDMA access from M4 core

ceggers — Wed, 31 Aug 2022 07:27:11 GMT

Why is the context data not visible in ARM RAM?

The SDMA has its own SRAM, this is distinct from the SRAMs of the ARM and the external DDR RAM. The RAM (and also the ROM, the SDMA core registers and parts of the status registers) is not visible from the ARM processor (e.g. these resources are directly tied to the SDMA CPU and not connected to any busses of the ARM).

<Advertising>With a SDMA debugger, you have full access to all resources of the SDMA</Advertising>

Re: SDMA access from M4 core

LennartB — Wed, 31 Aug 2022 08:14:47 GMT

Hi Christian,

Thanks for your prompt response.

I assumed that it is possible to use the "C0_GETCTXT" command to transfer the context from SDMA RAM to ARM RAM (just to see if it works). Otherwise it should be possible to use "C0_SETCTX" to do it the other way around, right?

I can try the "C0_SETCTX" command and see with the JTAG whether the SDMA RAM is affected.

Regards,

Lennart

Re: SDMA access from M4 core

ceggers — Wed, 31 Aug 2022 08:20:34 GMT

I can try the "C0_SETCTX" command and see with the JTAG whether the SDMA RAM is affected.

Yes, that's no problem. You can also debug the C0_SETCTX routine itself, but therefore the routine must be linked into RAM (no breakpoints can be set in ROM).

Do you own a JTAG Debugger from Lauterbach?

regards
Christian

Re: SDMA access from M4 core

LennartB — Wed, 31 Aug 2022 08:58:58 GMT

I am unfamiliar with debuggers from Lauterbach. Currently, I am using the Segger JLink for debugging the M4 core.

Best regards,
Lennart

Re: SDMA access from M4 core

ceggers — Wed, 31 Aug 2022 11:31:08 GMT

The Lauterbach debugger is the only I know where you can Debug the SDMA. Currently there are even two possibilities:

Lauterbach offers SDMA support as a license option
I have written an extension for SDMA myself (see Screenshot here).

regards,
Christian