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    <title>topic i.MX8M Plus SDMA3 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1510606#M194202</link>
    <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I tried the provided CMSIS example from the M7 SDK (cmsis_ecspi_sdma_loopback_transfer) and it is working well, utilizing SPI2 and SDMA1. Since SDMA1 is already used by Linux I would like to switch to SDMA3 which is reserved for the M7. I tried changing the definitions in the mentioned example:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;DRIVER_MASTER_SPI_DMA_BASE in &lt;STRONG&gt;cmsis_ecspi_sdma_loopback_transfer.c&lt;/STRONG&gt;&lt;/LI&gt;&lt;LI&gt;RTE_SPI2_DMA_TX_DMA_BASE and RTE_SPI2_DMA_RX_DMA_BASE in &lt;STRONG&gt;RTE_Device.h&lt;/STRONG&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;but the example stopped working. It finishes the DRIVER_MASTER_SPI.Transfer call but never executes the transfer. There is no output on the SPI pins and the ECSPI_MasterSignalEvent_t is never called.&lt;/P&gt;&lt;P&gt;Is it possible to use SPI with SDMA3?&lt;/P&gt;&lt;P&gt;Do I have to change any other definition to use SDMA3 instead of SDMA1?&lt;/P&gt;&lt;P&gt;Is there some additional clock that needs to be enabled?&lt;/P&gt;&lt;P&gt;PS. I tried also with SDMA2 and had the same issue.&lt;/P&gt;</description>
    <pubDate>Wed, 24 Aug 2022 05:45:02 GMT</pubDate>
    <dc:creator>JakaKordez</dc:creator>
    <dc:date>2022-08-24T05:45:02Z</dc:date>
    <item>
      <title>i.MX8M Plus SDMA3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1510606#M194202</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I tried the provided CMSIS example from the M7 SDK (cmsis_ecspi_sdma_loopback_transfer) and it is working well, utilizing SPI2 and SDMA1. Since SDMA1 is already used by Linux I would like to switch to SDMA3 which is reserved for the M7. I tried changing the definitions in the mentioned example:&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;DRIVER_MASTER_SPI_DMA_BASE in &lt;STRONG&gt;cmsis_ecspi_sdma_loopback_transfer.c&lt;/STRONG&gt;&lt;/LI&gt;&lt;LI&gt;RTE_SPI2_DMA_TX_DMA_BASE and RTE_SPI2_DMA_RX_DMA_BASE in &lt;STRONG&gt;RTE_Device.h&lt;/STRONG&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;but the example stopped working. It finishes the DRIVER_MASTER_SPI.Transfer call but never executes the transfer. There is no output on the SPI pins and the ECSPI_MasterSignalEvent_t is never called.&lt;/P&gt;&lt;P&gt;Is it possible to use SPI with SDMA3?&lt;/P&gt;&lt;P&gt;Do I have to change any other definition to use SDMA3 instead of SDMA1?&lt;/P&gt;&lt;P&gt;Is there some additional clock that needs to be enabled?&lt;/P&gt;&lt;P&gt;PS. I tried also with SDMA2 and had the same issue.&lt;/P&gt;</description>
      <pubDate>Wed, 24 Aug 2022 05:45:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1510606#M194202</guid>
      <dc:creator>JakaKordez</dc:creator>
      <dc:date>2022-08-24T05:45:02Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Plus SDMA3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1519006#M194903</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/205447"&gt;@JakaKordez&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Could you please provide me with the BSP versions of u-boot and linux-imx that you are using?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Dhruvit.&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2022 05:38:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1519006#M194903</guid>
      <dc:creator>Dhruvit</dc:creator>
      <dc:date>2022-09-08T05:38:02Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Plus SDMA3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1519030#M194907</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/201299"&gt;@Dhruvit&lt;/a&gt; ,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The BSP is from the Avnet Embedded board i.MX8M Plus:&lt;/P&gt;&lt;P&gt;- U-boot version is 2021.04-5.10.35-2.0.0&lt;/P&gt;&lt;P&gt;- Linux kernel version is 5.10.35-lts-5.10.y&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards&lt;/P&gt;&lt;P&gt;Jaka&lt;/P&gt;</description>
      <pubDate>Thu, 08 Sep 2022 06:21:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1519030#M194907</guid>
      <dc:creator>JakaKordez</dc:creator>
      <dc:date>2022-09-08T06:21:27Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Plus SDMA3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1524320#M195317</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/205447"&gt;@JakaKordez&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Could you please try changing the following for &lt;EM&gt;SDMA1&lt;/EM&gt;,&lt;/P&gt;
&lt;P&gt;Kindly comment the &lt;EM&gt;"CONFIG_IMX8MP"&amp;nbsp;&lt;/EM&gt;from two lines of the &lt;EM&gt;"/arch/arm/mach-imx/spl.c"&lt;/EM&gt; file.&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;#Line No. 350 and #Line No. 416:&lt;/EM&gt;&lt;/P&gt;
&lt;P&gt;#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MN)&amp;nbsp;&lt;/P&gt;
&lt;P&gt;And comment out the i.MX8MP part:&lt;/P&gt;
&lt;P&gt;#if &lt;STRONG&gt;/*&lt;/STRONG&gt;defined(CONFIG_IMX8MP) || */ defined(CONFIG_IMX8MN&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;BR /&gt;Dhruvit.&lt;/P&gt;</description>
      <pubDate>Tue, 20 Sep 2022 14:40:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1524320#M195317</guid>
      <dc:creator>Dhruvit</dc:creator>
      <dc:date>2022-09-20T14:40:50Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Plus SDMA3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1525504#M195408</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am sorry, there is no spl.c file in the mentioned folder in our Linux source.&lt;/P&gt;&lt;P&gt;In the meantime I think I already figured out the answers to my questions. Based on the memory map of i.MX 8M Plus reference manual (chapter 2.4), only the SDMA1 has SPI devices mapped to its address space. SDMA2 and SDMA3 are reserved for audio interfaces.&lt;/P&gt;</description>
      <pubDate>Wed, 21 Sep 2022 05:17:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1525504#M195408</guid>
      <dc:creator>JakaKordez</dc:creator>
      <dc:date>2022-09-21T05:17:12Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M Plus SDMA3</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1525606#M195420</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/205447"&gt;@JakaKordez&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;Sorry for not specifying earlier, but the spl.c was referenced for the u-boot source.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Note: If the query has been resolved please accept the reply as the solution!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thank you,&lt;BR /&gt;Best Regards,&lt;BR /&gt;Dhruvit.&lt;/P&gt;</description>
      <pubDate>Wed, 21 Sep 2022 07:14:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-SDMA3/m-p/1525606#M195420</guid>
      <dc:creator>Dhruvit</dc:creator>
      <dc:date>2022-09-21T07:14:22Z</dc:date>
    </item>
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