https://community.nxp.com/t5/i-MX-Processors/iMX8M-Plus-Ethernet-Design-Question/m-p/1506175#M193858 <P>Hi NXP,</P><P>Our team want to design the ethernet as follow, Is it possible controlling ethernet by this method ?</P><P>M7 use the serial interface(SPI/QSPI) sending PHY configuration data to FPGA, the FPGA will control the PHY MIDO/MDC by M7's PHY data.&nbsp;</P><P>Thanks.&nbsp;</P><P>FPGA - MDIO/MDC</P><P>M7 - RGMII TX / RGMII RX</P><P>&nbsp; &nbsp; &nbsp; - SERIAL INTERFACE (SPI, QSPI)</P><P>&nbsp;</P><P>Best Regards,</P><P>Wayne.</P> Mon, 15 Aug 2022 13:00:41 GMT waynechung2 2022-08-15T13:00:41Z https://community.nxp.com/t5/i-MX-Processors/iMX8M-Plus-Ethernet-Design-Question/m-p/1506175#M193858 <P>Hi NXP,</P><P>Our team want to design the ethernet as follow, Is it possible controlling ethernet by this method ?</P><P>M7 use the serial interface(SPI/QSPI) sending PHY configuration data to FPGA, the FPGA will control the PHY MIDO/MDC by M7's PHY data.&nbsp;</P><P>Thanks.&nbsp;</P><P>FPGA - MDIO/MDC</P><P>M7 - RGMII TX / RGMII RX</P><P>&nbsp; &nbsp; &nbsp; - SERIAL INTERFACE (SPI, QSPI)</P><P>&nbsp;</P><P>Best Regards,</P><P>Wayne.</P> Mon, 15 Aug 2022 13:00:41 GMT https://community.nxp.com/t5/i-MX-Processors/iMX8M-Plus-Ethernet-Design-Question/m-p/1506175#M193858 waynechung2 2022-08-15T13:00:41Z