topic Re: iMX6ULL DDR IO pad reassignment in i.MX Processors

iMX6ULL DDR IO pad reassignment

mobileoverlord — Tue, 09 Aug 2022 00:17:26 GMT

According to the Hardware design guide Section 3.5.1 discusses data line swapping for the DDR routing configuration. It has the following note:

If the byte lane swapping was done, the target DDR IC register read value must be transposed according to the data line swapping.

The Hardware reference IO pin max configuration section 4.1.1 describes the MMDC DATA* pins are muxed to their corresponding pads with No Mixing (ALT0). I am under the impression that I need to remap this pin to pad mux to reflect the four data line swaps that were made in the custom layout I am working with. In my layout D1 & D4 are swapped and D2 & D7 are swapped. Please advise what changes need to be reflected in the registers. Thanks!

Re: iMX6ULL DDR IO pad reassignment

mobileoverlord — Tue, 09 Aug 2022 00:58:19 GMT

sorry, I think I misunderstood the requirements. I believe I only need to ensure the pad configuration is set for all DDR data pins in use. The bit swapping will “just work”

Re: iMX6ULL DDR IO pad reassignment

Sanket_Parekh — Wed, 31 Aug 2022 14:49:00 GMT

Hi @mobileoverlord

I hope you are doing well.

I think your issue is resolved. Can i mark this ticket to close state?

Thanks & Regards

Sanket Parekh

Re: iMX6ULL DDR IO pad reassignment

mobileoverlord — Wed, 31 Aug 2022 16:09:54 GMT

Should be OK thanks