i.MX Processors中的主题 Re: OV5642 camera PLL settings problem (on sabdresd board)

OV5642 camera PLL settings problem (on sabdresd board)

Selea — Fri, 25 Jan 2013 15:40:03 GMT

WE are using a module(made by us) with the ov5642 sensor (supported in the sabdr SD board bsp).

starting it with it's default values (initila_values table in the ov5642.c) it works fine with VGA resolution and 30 fps (PCLK is 48Mhz from 24Mhz mclk derived from the MX6Q).

But when we try to change capture mode to any other , the PLL seem to fail.

I mean the driver load a new register table where there are new pll register settings, and what we have is a very very very unstable PCLK with a wrong value (maybe 5- 10 Mhz) and of course fps is wrong , image is crappy.... etc etc etc...

WE made some test and the problem is in the tables (we tested almost all mode present in the driver).

We tried to reload always the initial_values table, and it works fine. We made this test to understand if the problem was in the operation to change mode or

in the table values then the problem is in the table value that set the pll in a bad status.

It could be the values or the sequence used to set the values .....

On the ov5642 data sheet i didn't find a lot about pll usage and precaution to change its values, i found just the register meanig (and not so clearley explined)...

So i don't know if there is any special sequence to change its settings...

Thanks

Omar

Re: OV5642 camera PLL settings problem (on sabdresd board)

daiane_angolini — Mon, 28 Jan 2013 12:24:16 GMT

Sorry, I was not able to complete understand your problem.

But, ov5642 driver worked for all capture modes. I have worked a lot with camera input and several capture modes some time ago, using imx53, and I have never got a problem on any capture mode from driver.

So, I don´t think those table are wrong. (otherwise, I would had faced problems as well).

Do you know your clock tree? What is your camera clock parent?

Re: OV5642 camera PLL settings problem (on sabdresd board)

Selea — Mon, 28 Jan 2013 15:37:19 GMT

Hi,

I'm not sure if the driver (ov5642.c) is the same. The one on the BSP for imx6q is different from the one you find in other git.

anyway the mclk is 24Mhz and come from the im6q.

I try to exaplain what is happening.

At the beginning the driver load a regiser table called initial_values (and it is a 30 fps VGA) the there is another table called 30fps VGA, used when coming from another mode to vga 30fps... and it doesn't work, but if i try to reload the init table when i select the mode 0 (vga 30fps) it works.

I tried also to load the 15 fps vga (there is its table) and it doesn't works... So i treid to change modify the initial value table to have the vga 15 fps: i just changed the sysclk divider (register 0x3010) in the inital values table, and it works.

So i was able to change mode from 30 fos vga to 15 fps vga.

now i tried to change from vga to qvga, in this situation (from vga to qvga) the driver loads a very small table (just 5 registers)

4 register set the output windows (to QVGA values) and the 0x3815 that shouls be the PCLK divider.... well it doesn' twork... again i have very strange behaviour in the outbput.

... I think that could it be our module (we did the ov5642) but it is a very simple module with power supply, i2C connection and digital video port .... SO i don't know what coudl be wrong, there is any schematics example on the ov5642 module?

Just to understand if it could be an hardware issue.

Re: OV5642 camera PLL settings problem (on sabdresd board)

daiane_angolini — Tue, 29 Jan 2013 13:07:33 GMT

hum....

For ov5642 table, I think you must contact omnvision. Everytime I needed a new capture mode table I asked them.

I know imx6 sabre lite has some camera module, and I think it´s ov5642. Please, give it a try. But I think that imx would be responsible to provide the clock using some pin properly configured.

Re: OV5642 camera PLL settings problem (on sabdresd board)

Selea — Tue, 29 Jan 2013 13:10:50 GMT

yes it is. the clock (24Mhz) is correctc and it comes from the imx6q.... there are some wronge settinng in some registers that bring to strange behaviour on the parallel video output... maybe the ov5640 was tested only with mipi interface? (the same of 5642)... i'm checking them..

Re: OV5642 camera PLL settings problem (on sabdresd board)

daiane_angolini — Tue, 29 Jan 2013 13:30:08 GMT

I never remember by heart what was formally tested on each release (you need to take a look on release notes).

But, I have worked with ov5246 with CSI internface on imx53 SMD and imx6 sabre lite. (but it was 3.0.15 kernel for imx6 instead of 3.0.35)

Re: OV5642 camera PLL settings problem (on sabdresd board)

Selea — Tue, 29 Jan 2013 13:37:26 GMT

i will have a sabre lite next week with the ov5642 module... so i will test on it. Now we are working with sabre SD and with a home made ov5642 module (but i wonder what could be wrong on the hardware to have such kind of behaviour....) there is just the sensor, the power supply and connector....

Re: OV5642 camera PLL settings problem (on sabdresd board)

lily_zhang — Tue, 29 Jan 2013 14:13:44 GMT

I think you had better double check the register settings in your new table.

Re: OV5642 camera PLL settings problem (on sabdresd board)

Selea — Tue, 29 Jan 2013 14:20:38 GMT

i found the first hardware issue. In the register table they disable the internal regulator. (in our hardware we must use the internal because we don't have any external), but the sttrange is that in the initial values it is enable... (it shoudl not if the external i spresent....). now i modify the table enabling it, i will tell you what happen. compiling......

Re: OV5642 camera PLL settings problem (on sabdresd board)

adc1 — Thu, 06 Nov 2014 09:16:15 GMT

Hi,

have you solved in anyway this issue? I'm facing a similar problem with a ov5640_mipi camera, I obtain a very slow fps in capture mode with a 24Mhz mclk from MX6Q and I don't know what to check!
I'm using a 3.0.35 kernel with standard ov5640_mipi.c driver, I haven't changed anything in registry configuration but, for example, I obtain 1fps in 1920x1080 capture mode instead of 30fps. Could you help me?

thank you

regards

Andrea

Re: OV5642 camera PLL settings problem (on sabdresd board)

Selea — Thu, 06 Nov 2014 09:33:31 GMT

mine is working now.

on mipi there was a bug on clk settings..... (let me check if i could find the patch..)

check the mipi clk freq from sensor just to start.

Omar

Re: OV5642 camera PLL settings problem (on sabdresd board)

Selea — Thu, 06 Nov 2014 09:40:38 GMT

the patch I had from boundary was for 3.10.17 ... with 3.0.35 works fine (just changed the register for activate the internal voltage regulator in my hardware.

check the mipi clks and the MCLK that is going from imx6 to the mipi sensor (all the clks are derived from that one).

Omar

Re: OV5642 camera PLL settings problem (on sabdresd board)

adc1 — Thu, 06 Nov 2014 09:45:53 GMT

thank you Omar for your fast reply,

I'm going to check these clks and I let you know

regards

Andrea

Re: OV5642 camera PLL settings problem (on sabdresd board)

adc1 — Thu, 06 Nov 2014 13:23:53 GMT

Hi Omar,

I have verified that imx6 mclk is setup at 24MHz.

static struct fsl_mxc_camera_platform_data ov5640_mipi_data = {

.mclk = 24000000,

.csi = 0,

.io_init = ov5640_mipi_camera_io_init,

.pwdn = ov5640_mipi_camera_powerdown,

};

now PLL registers are configured as follows: 0x3034=0x18, 0x3035=0x11, 0x3036=0x54, 0x3037=0x13.

With these values I obtain (seeing at OV5640_get_sysclk ov5640_mipi.c function) a VCO of 67.2MHz and a sysclk of 8.4MHz (in 1920x1080 format at 30fps mode). Are these correct values?

Could you give me a correct configuration of these registers to obtain a correct fps? Have I to focus to other registers to check the framerate?

If I try to update that register to increase sysclk MHz I obtain kernel errors (Division by zero in kernel) cause some registers are read as 0x00

thank you again for your attention,

regards

Andrea

Re: OV5642 camera PLL settings problem (on sabdresd board)

Raana — Mon, 16 May 2016 08:34:01 GMT

Hi Omar,

I'm facing same kind of issue in OV5640 CMOS sensor. (Not a MIPI)

fOSC = 26MHz
driver path: drivers/media/i2c/soc_camera/ov5640.c
kernel version: L3.10.31
By default, ov5640 driver file is not there. so, I have derived it from OV5642.

Now the problem is,
All the resolutions (QVGA, VGA, 720p and 1080p) are working fine If I'm running overlay by using gst-launch.
But, when I'm trying to capture the data by using gst-launch the captured frame is not coming properly (i.e. stuck, run, stuck and run ) for 720p and 1080p but it's working fine with QVGA and VGA resolutions.

What may be the issue ?
If it's possible, Can you share me the 720p and 1080p register settings for ov5640 or ov5640.c driver file.

Please guide me to go further.
Thanks in Advance.

Regards,

J.P.Raja

Re: OV5642 camera PLL settings problem (on sabdresd board)

RutvijTrivedi207 — Sat, 06 Dec 2025 12:16:26 GMT

Most likely causes for OV5642 PLLs failing when switching modes: wrong PLL register values, missing required write order/delays, or unstable clocks/reset/power while you reprogram the PLL. Quick checklist to try now:

Stop streaming, ensure MCLK & supplies stable (wait a few ms after rails/reset).
Write PLL regs first, then poll lock (or wait a few ms) before writing timing/frame regs — sequence matters.
Readback every PLL reg after write to confirm the sensor accepted the values.
Ensure you aren’t changing PLL while SoC re-parents clocks or during DVFS/display events.
Check for register page/bank switch mistakes in your table (very common).
If initial_values works, copy its exact ordering/timing and apply to the other mode tables — often the content is OK, sequence is the issue.

If you want examples of how upstream bring-ups handle regulator/clock ordering and mode sequencing, these real upstream commits are useful reference material:
https://web.git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=fa9e6df636fb8b3b27570f38c53640c9e2b02f79

https://github.com/zephyrproject-rtos/zephyr/commit/c784481ca039ccd606a192ee07bc83f6b0117e59
https://web.git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=9d382f6a9978916317b3fb4ef07b5fec684adde0

For a compact design/read-up that shows the same sequencing and checks in a pipeline context see our implementation notes here (purely technical reference): https://siliconsignals.io/blog/v4l2-camera-stack-step-by-step-guide-for-custom-devices/

If you paste the exact register write sequence (timestamps) for a failing mode plus the working initial_values writes, may we can get more help.

--
thanks