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    <title>topic Re: Power up/down sequence in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1490818#M192645</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;For&amp;nbsp;&lt;SPAN class=""&gt;MIMXRT1051CVL5B, c&lt;/SPAN&gt;an you please review my low-level power architecture (picture below) to the NXP to verify I didn't miss something?&lt;/P&gt;&lt;P&gt;Are there any power up/down requirements besides that the VDD_SNVS_IN should power up first?&lt;/P&gt;&lt;P&gt;Are there any timing requirements that I miss in the datasheet?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="sapirbuz_1-1658043376484.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186888i02D2AC61866CCFF7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="sapirbuz_1-1658043376484.png" alt="sapirbuz_1-1658043376484.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 18 Jul 2022 06:54:50 GMT</pubDate>
    <dc:creator>sapirbuz</dc:creator>
    <dc:date>2022-07-18T06:54:50Z</dc:date>
    <item>
      <title>Power up/down sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1490603#M192623</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 17 Jul 2022 07:33:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1490603#M192623</guid>
      <dc:creator>sapirbuz</dc:creator>
      <dc:date>2022-07-17T07:33:29Z</dc:date>
    </item>
    <item>
      <title>Re: Power up/down sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1490735#M192637</link>
      <description>&lt;P&gt;I don't know what board you are talking about, but you can refer to the data sheet to get information&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 18 Jul 2022 04:49:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1490735#M192637</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2022-07-18T04:49:42Z</dc:date>
    </item>
    <item>
      <title>Re: Power up/down sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1490818#M192645</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;For&amp;nbsp;&lt;SPAN class=""&gt;MIMXRT1051CVL5B, c&lt;/SPAN&gt;an you please review my low-level power architecture (picture below) to the NXP to verify I didn't miss something?&lt;/P&gt;&lt;P&gt;Are there any power up/down requirements besides that the VDD_SNVS_IN should power up first?&lt;/P&gt;&lt;P&gt;Are there any timing requirements that I miss in the datasheet?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="sapirbuz_1-1658043376484.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186888i02D2AC61866CCFF7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="sapirbuz_1-1658043376484.png" alt="sapirbuz_1-1658043376484.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 18 Jul 2022 06:54:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1490818#M192645</guid>
      <dc:creator>sapirbuz</dc:creator>
      <dc:date>2022-07-18T06:54:50Z</dc:date>
    </item>
    <item>
      <title>Re: Power up/down sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1491041#M192659</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200625"&gt;@sapirbuz&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;About the RT1050 power up and power down sequence, please refer to this document:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=MIMXRT105060HDUG&amp;amp;location=null" target="_blank"&gt;https://www.nxp.com/webapp/Download?colCode=MIMXRT105060HDUG&amp;amp;location=null&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="kerryzhou_0-1658145554330.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186994i01947A77D4683839/image-size/medium?v=v2&amp;amp;px=400" role="button" title="kerryzhou_0-1658145554330.png" alt="kerryzhou_0-1658145554330.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="kerryzhou_1-1658145568663.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186995iEFE8FF43012AC289/image-size/medium?v=v2&amp;amp;px=400" role="button" title="kerryzhou_1-1658145568663.png" alt="kerryzhou_1-1658145568663.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;datasheet also has some information:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="kerryzhou_2-1658145603132.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186996iB451B714E5874A80/image-size/medium?v=v2&amp;amp;px=400" role="button" title="kerryzhou_2-1658145603132.png" alt="kerryzhou_2-1658145603132.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="kerryzhou_3-1658145616400.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/186997i84214E9F5E450CEB/image-size/medium?v=v2&amp;amp;px=400" role="button" title="kerryzhou_3-1658145616400.png" alt="kerryzhou_3-1658145616400.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Wish it helps you!&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;kerry&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 18 Jul 2022 12:00:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1491041#M192659</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-07-18T12:00:46Z</dc:date>
    </item>
    <item>
      <title>Re: Power up/down sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1505860#M193813</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;My architecture is described in the picture below:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="sapirbuz_0-1660501559168.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/190142i590C977D59C1E9D1/image-size/medium?v=v2&amp;amp;px=400" role="button" title="sapirbuz_0-1660501559168.png" alt="sapirbuz_0-1660501559168.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It means that the SNVS_IN will be the first to turn off.&amp;nbsp;&lt;/P&gt;&lt;P&gt;Will the following architecture solve that problem?:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="sapirbuz_1-1660501905469.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/190143i1032F590A8371E69/image-size/medium?v=v2&amp;amp;px=400" role="button" title="sapirbuz_1-1660501905469.png" alt="sapirbuz_1-1660501905469.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sun, 14 Aug 2022 18:32:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1505860#M193813</guid>
      <dc:creator>sapirbuz</dc:creator>
      <dc:date>2022-08-14T18:32:31Z</dc:date>
    </item>
    <item>
      <title>Re: Power up/down sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1505897#M193819</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200625"&gt;@sapirbuz&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; From the requirement:&lt;/P&gt;
&lt;P&gt;• Power Up Sequence Requirement&lt;BR /&gt;— VDD_SNVS_IN supply must be turned on before any other power supply or be connected (shorted) with VDD_HIGH_IN supply&lt;/P&gt;
&lt;P&gt;• Power Down Sequence Requirement&lt;BR /&gt;— VDD_SNVS_IN supply must be turned off after any other power supply or be connected (shorted) with VDD_HIGH_IN supply&lt;/P&gt;
&lt;P&gt;You can connect it together.&lt;/P&gt;
&lt;P&gt;If you have any other questions, welcome to create the new question post, thanks, as this post already opened for more than one month.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Kerry&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 15 Aug 2022 02:16:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1505897#M193819</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-08-15T02:16:16Z</dc:date>
    </item>
    <item>
      <title>Re: Power up/down sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1505985#M193832</link>
      <description>&lt;P&gt;Thank you!&lt;/P&gt;&lt;P&gt;So when I connect those pins together, the power up/down sequence rules are canceled and I can power up/down in the sequence I want?&lt;/P&gt;</description>
      <pubDate>Mon, 15 Aug 2022 05:57:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1505985#M193832</guid>
      <dc:creator>sapirbuz</dc:creator>
      <dc:date>2022-08-15T05:57:52Z</dc:date>
    </item>
    <item>
      <title>Re: Power up/down sequence</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1505999#M193838</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200625"&gt;@sapirbuz&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="kerryzhou_0-1660544005225.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/190164i79C7E52A6BC1D8A6/image-size/medium?v=v2&amp;amp;px=400" role="button" title="kerryzhou_0-1660544005225.png" alt="kerryzhou_0-1660544005225.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;The above sequence not canceled, just&amp;nbsp; VDD_SNVS_IN and VDD_HIGH_IN can be together.&lt;/P&gt;
&lt;P&gt;Other sequence still need to follow.&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Kerry&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 15 Aug 2022 06:14:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Power-up-down-sequence/m-p/1505999#M193838</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-08-15T06:14:54Z</dc:date>
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