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    <title>topic Re: WDOG in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/WDOG/m-p/1489320#M192525</link>
    <description>&lt;P&gt;Which product are you using? Generally for the reset circuit recommend to use the reference design we supply.&lt;/P&gt;</description>
    <pubDate>Thu, 14 Jul 2022 08:47:07 GMT</pubDate>
    <dc:creator>Rita_Wang</dc:creator>
    <dc:date>2022-07-14T08:47:07Z</dc:date>
    <item>
      <title>WDOG</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/WDOG/m-p/1479271#M191857</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;We would like to use the external WDOG signal to power down the circuit, like in the evaluation board (see picture below); but in our design, the WDOG will not reset the SD0 and SD1 blocks. is that ok?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="sapirbuz_0-1656009147260.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/184444iDB78158CE9180456/image-size/medium?v=v2&amp;amp;px=400" role="button" title="sapirbuz_0-1656009147260.png" alt="sapirbuz_0-1656009147260.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 23 Jun 2022 18:36:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/WDOG/m-p/1479271#M191857</guid>
      <dc:creator>sapirbuz</dc:creator>
      <dc:date>2022-06-23T18:36:25Z</dc:date>
    </item>
    <item>
      <title>Re: WDOG</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/WDOG/m-p/1489320#M192525</link>
      <description>&lt;P&gt;Which product are you using? Generally for the reset circuit recommend to use the reference design we supply.&lt;/P&gt;</description>
      <pubDate>Thu, 14 Jul 2022 08:47:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/WDOG/m-p/1489320#M192525</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2022-07-14T08:47:07Z</dc:date>
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