https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-ADV7481-Analog-Input-issue/m-p/1484425#M192176 <P>In our current project using iMX8M Plus, we need to use both MIPI-CSI2 ports connected to an ADV7481 chip, one for HDMI (already working) and another for Analog input.</P><P>We managed to properly build both video pipelines in v4l2 by fixing some issues in imx8-mipi-csi2-sam.c file.</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="graph_txa_txb.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/185542iBBDDFC7DF5EF7B7F/image-size/medium?v=v2&amp;px=400" role="button" title="graph_txa_txb.png" alt="graph_txa_txb.png" /></span></P><P>Streaming on HDMI pipeline is working properly but there are no frames detected on the Analog pipeline.</P><P>This issue seems similar to one we had a few month ago with HDMI and which was related to HS_SETTLE settings.</P><P>The measured mipi clk signal at the MIPI-CSI2 input port is 100 MHz and verification has been done that there is some activity on data lane.</P><P>Different hs_settle settings from 1 to 31 have been tested without success.</P><P>See attached MIPI-DPHY status logs.</P><P>CSIS_DPHYSTATUS toggles between 0xe2 and 0xf1 but the expected value should be 0xe0 (we only use 1 lane on the second MIPI-CSI2 port).</P><P>Can you please help us to find what can cause this issue here. Are the settings different on the second MIPI-CSI2 port ?</P> Tue, 05 Jul 2022 07:10:01 GMT Brt 2022-07-05T07:10:01Z https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-ADV7481-Analog-Input-issue/m-p/1484425#M192176 <P>In our current project using iMX8M Plus, we need to use both MIPI-CSI2 ports connected to an ADV7481 chip, one for HDMI (already working) and another for Analog input.</P><P>We managed to properly build both video pipelines in v4l2 by fixing some issues in imx8-mipi-csi2-sam.c file.</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="graph_txa_txb.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/185542iBBDDFC7DF5EF7B7F/image-size/medium?v=v2&amp;px=400" role="button" title="graph_txa_txb.png" alt="graph_txa_txb.png" /></span></P><P>Streaming on HDMI pipeline is working properly but there are no frames detected on the Analog pipeline.</P><P>This issue seems similar to one we had a few month ago with HDMI and which was related to HS_SETTLE settings.</P><P>The measured mipi clk signal at the MIPI-CSI2 input port is 100 MHz and verification has been done that there is some activity on data lane.</P><P>Different hs_settle settings from 1 to 31 have been tested without success.</P><P>See attached MIPI-DPHY status logs.</P><P>CSIS_DPHYSTATUS toggles between 0xe2 and 0xf1 but the expected value should be 0xe0 (we only use 1 lane on the second MIPI-CSI2 port).</P><P>Can you please help us to find what can cause this issue here. Are the settings different on the second MIPI-CSI2 port ?</P> Tue, 05 Jul 2022 07:10:01 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-ADV7481-Analog-Input-issue/m-p/1484425#M192176 Brt 2022-07-05T07:10:01Z https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-ADV7481-Analog-Input-issue/m-p/1497186#M193146 <P>&gt; We managed to properly build both video pipelines in v4l2 by fixing some issues in imx8-mipi-csi2-sam.c file.</P><P>&nbsp;</P><P>Could you please share your fixes?</P><P>I'm trying to do exactly this (HDMI input through ADV7481) and I would be grateful for any information on this (so far it stops on building v4l2 pipeline due to pad mismatches)</P> Thu, 28 Jul 2022 09:08:09 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-ADV7481-Analog-Input-issue/m-p/1497186#M193146 akochubey 2022-07-28T09:08:09Z