topic Re: inline ECC in i.MX8M Plus in i.MX Processors

inline ECC in i.MX8M Plus

anhui527 — Fri, 15 Jan 2021 09:49:04 GMT

Hi, NXP experts are there any documents about the function of inline ECC in i.MX8M plus ? thanks.

inline ECC in i.MX8M Plus

joanxie — Fri, 15 Jan 2021 10:36:48 GMT

don't find any document for this, but get the information from expert team:
"The 8M Plus will support the DRAM inline ECC feature, however, it is currently being validated. Once validation is complete further information on the support will be made available.

This is an optional feature and customers will be allowed to enable or disable as well as configure the regions they want to be ECC protected. When enabled there will be a portion of DRAM (up to 1/8th the total density) that will have to be reserved. Also, there are performance and boot time implications with the feature enabled. For Inline ECC, 64/8 SECDED Hamming code is used and Data to ECC ratio is 8/1"

Re: inline ECC in i.MX8M Plus

Anishamd — Thu, 23 Jun 2022 05:07:32 GMT

how do we enable ECC in i.MX8M Plus can you share any documents if you have.

Re: inline ECC in i.MX8M Plus

bernhardfink — Fri, 21 Jun 2024 08:08:56 GMT

Inline ECC in i.MX 8M Plus can be enabled (and tested) using the DDR Configuration tool in the i.MX Config Tool.

https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/config-tools-for-i-mx-applications-processors:CONFIG-TOOLS-IMX