https://community.nxp.com/t5/i-MX-Processors/How-to-generate-i-MX8MP-LPDDR4-initialisation/m-p/1478249#M191804 <P>We are trying to generate the SPL <EM>lpddr4_timing.c</EM> using the <EM>MX8M_DDR_tool</EM> for our own hardware PCB design incorporating Micron's <SPAN class="">MT53E512M32D1</SPAN> (LP4DDR). In the MX8M_DDR_tool package, we found the example <EM>script\mx8mp\mx8mp_lpddr4_2gb_2000m_200m_50m_32bit_2cs_v6.ds</EM>, which serves as a starting point. However, we do not know yet how to modify this script for our LPDDR4 RAM.</P><P>Questions: can anyone provide a configuration for the <SPAN class="">MT53E512M32D1? Does anyone have the DS RAM init script for the LPDDR4 assembled on the 8MPLUS evaluation board so that we can see the differences?</SPAN></P><P><SPAN class="">Thank you and best wishes<BR />Peter</SPAN></P> Wed, 22 Jun 2022 14:29:24 GMT peter_voser 2022-06-22T14:29:24Z https://community.nxp.com/t5/i-MX-Processors/How-to-generate-i-MX8MP-LPDDR4-initialisation/m-p/1478249#M191804 <P>We are trying to generate the SPL <EM>lpddr4_timing.c</EM> using the <EM>MX8M_DDR_tool</EM> for our own hardware PCB design incorporating Micron's <SPAN class="">MT53E512M32D1</SPAN> (LP4DDR). In the MX8M_DDR_tool package, we found the example <EM>script\mx8mp\mx8mp_lpddr4_2gb_2000m_200m_50m_32bit_2cs_v6.ds</EM>, which serves as a starting point. However, we do not know yet how to modify this script for our LPDDR4 RAM.</P><P>Questions: can anyone provide a configuration for the <SPAN class="">MT53E512M32D1? Does anyone have the DS RAM init script for the LPDDR4 assembled on the 8MPLUS evaluation board so that we can see the differences?</SPAN></P><P><SPAN class="">Thank you and best wishes<BR />Peter</SPAN></P> Wed, 22 Jun 2022 14:29:24 GMT https://community.nxp.com/t5/i-MX-Processors/How-to-generate-i-MX8MP-LPDDR4-initialisation/m-p/1478249#M191804 peter_voser 2022-06-22T14:29:24Z