https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476550#M191652 <P>can the boot mode pins be sampled according to the defined internal pull-up pull-down? or must we place external PU/PD?</P><DIV class=""><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="sapirbuz_0-1655709082274.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/183869iBDC7E7C64F07EA4D/image-size/medium?v=v2&amp;px=400" role="button" title="sapirbuz_0-1655709082274.png" alt="sapirbuz_0-1655709082274.png" /></span><P>&nbsp;</P></DIV> Mon, 20 Jun 2022 07:11:36 GMT sapirbuz 2022-06-20T07:11:36Z https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476255#M191616 <P>Hi,</P><P>&nbsp;</P><P><SPAN class="">MIMXRT1051CVL5B.</SPAN></P><P><SPAN class="">We would like to use 2 boot options on our design: boot from fuse and boot from serial downloader.</SPAN></P><P><SPAN class="">Must we keep the boot_mode[1,0] pins to define the boot mode on the fly? Or can we define it by SW and use the&nbsp;boot_mode[1,0] as GPIO for another purpose?</SPAN></P> Sat, 18 Jun 2022 13:49:34 GMT https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476255#M191616 sapirbuz 2022-06-18T13:49:34Z https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476342#M191627 <P>boot mode pins status is sampled once power-on, when chip is booted, you can use boot mode pins as GPIOs. we cannot switch boot mode by SW.</P> Mon, 20 Jun 2022 01:08:23 GMT https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476342#M191627 jay_heng 2022-06-20T01:08:23Z https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476550#M191652 <P>can the boot mode pins be sampled according to the defined internal pull-up pull-down? or must we place external PU/PD?</P><DIV class=""><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="sapirbuz_0-1655709082274.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/183869iBDC7E7C64F07EA4D/image-size/medium?v=v2&amp;px=400" role="button" title="sapirbuz_0-1655709082274.png" alt="sapirbuz_0-1655709082274.png" /></span><P>&nbsp;</P></DIV> Mon, 20 Jun 2022 07:11:36 GMT https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476550#M191652 sapirbuz 2022-06-20T07:11:36Z https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476565#M191657 <P>We must place external PU/PD. as IOMUXC cfg register will be reset when power-on</P> Mon, 20 Jun 2022 07:22:51 GMT https://community.nxp.com/t5/i-MX-Processors/boot-mode-pins/m-p/1476565#M191657 jay_heng 2022-06-20T07:22:51Z