PAD_UART2_RTS_B at low level by default

jfernandz — Thu, 16 Jun 2022 20:17:07 GMT

Hi everyone,

I'm trying to implement an RS-485 interface by using the UART2 in an i.MX6ULL, actually the UART2_DCE_TX, UART2_DCE_RX and UART2_DCE_CTS. The actual rs-485 transceiver I'm using is this LTC485. The UART2_DCE_CTS pin is connected to the DE pin of LTC485 transceiver, as you can see in this schema (LTC485 is the A1 IC):

Apparentely, when this is in that way ... the LTC485 sets the rx/tx diff at hight level (~5v3):

Like when you are writing in the bus... so this affects other equipments that are connected to this bus keeping them in a listening/reading state. And this happens until the OS boots and some application opens the port (/dev/ttymxc1).

I'm actually probing this CTS pin where the red arrow is placed (in the schematic) and I can see this CTS pin is in a high voltage state (~3v3):

I was wondering if playing with PAD_CTL settings for this pin I would get this CTS pin stays in a low voltage level until some application opens this serial port and this CTS pin behaves as usually does. This will prevent to introduce noise in the rs-485 bus.

This is my current DTS (regarding this UART2)

&iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; imx6ul-evk { pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x110b1 >; }; }; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; fsl,uart-has-rtscts; linux,rs485-enable-at-boot-time; status = "okay"; };

As you can see I've been playing around with this PAD_CTL config integer (0x110b1) trying to set a pull-down resistor of 100K Ohm as apparently this document and the i.MX 6ULL Applications Processor Reference Manual (pag 1819) suggests. However I still measure the CTS_B output with that 3v3 high level.

So I'm wondering if it's possible to achive this "low state by default" behavior by modifying this PAD_CTL register.

Thank you very much.

i.MX ProcessorsのトピックPAD_UART2_RTS_B at low level by default

PAD_UART2_RTS_B at low level by default