i.MX ProcessorsのトピックRe: SDRAM debugging is not happening on imxrt1051 processor target board

SDRAM debugging is not happening on imxrt1051 processor target board

venkataddagatla — Sun, 05 Jun 2022 14:22:18 GMT

We have connected SDRAM and NAND flash on semc bus on MIMXRT1051CVL5B target board. And We could not able to debug in SDRAM with the JLink script provided in SDK. However, we could able to debug in EVAL kit but not on our target board.

Kindly suggest the changes required in the jlink link script file.

PFA files.

Re: SDRAM debugging is not happening on imxrt1051 processor target board

jingpan — Mon, 06 Jun 2022 11:55:05 GMT

Hi @venkataddagatla ,

Can the RT1051 read/write SDRAM on your customer board?

Regards,

Jing

Re: SDRAM debugging is not happening on imxrt1051 processor target board

venkataddagatla — Tue, 07 Jun 2022 14:03:48 GMT

Yes , we have tested with the sample code evkbimxrt1050_semc on our target board and we able to read and write the from SDRAM but it is failing in the read write comparison.

The logs are attached.

SEGGER J-Link GDB Server V7.60b - Terminal output channel

SEMC SDRAM Example Start!

SEMC SDRAM Memory 32 bit Write Start, Start Address 0x80000000, Data Length 200 !

SEMC SDRAM Read 32 bit Data Start, Start Address 0x80000000, Data Length 200 !

SEMC SDRAM 32 bit Data Write and Read Compare Start!

SEMC SDRAM 32 bit Data Write and Read Compare Succeed!

SEMC SDRAM Memory 16 bit Write Start, Start Address 0x80000000, Data Length 4096 !

SEMC SDRAM Read 16 bit Data Start, Start Address 0x80000000, Data Length 4096 !

SEMC SDRAM 16 bit Data Write and Read Compare Start!

SEMC SDRAM 16 bit Data Write and Read Compare Failed!

SEMC SDRAM Memory 8 bit Write Start, Start Address 0x80000000, Data Length 4096 !

SEMC SDRAM Read 8 bit Data Start, Start Address 0x80000000, Data Length 4096 !

SEMC SDRAM 8 bit Data Write and Read Compare Start!

SEMC SDRAM 8 bit Data Write and Read Compare Failed!

SEMC SDRAM Example End.

Re: SDRAM debugging is not happening on imxrt1051 processor target board

jingpan — Thu, 09 Jun 2022 02:19:02 GMT

Hi @venkataddagatla ,

Can you share the schematic of this part?

Regards,

Jing

Re: SDRAM debugging is not happening on imxrt1051 processor target board

venkataddagatla — Thu, 09 Jun 2022 06:30:57 GMT

PFA

Re: SDRAM debugging is not happening on imxrt1051 processor target board

jingpan — Fri, 10 Jun 2022 06:51:23 GMT

Hi @venkataddagatla ,

NAND Flash CE# is shared with SDRAM A8. This is not allowed. Because the pins function is configured by IOCR.MUX_A8. After SEMC is well initialized, this field can't be changed.

I have a W9825 DCD file. You can take a look.

Regards,

Jing

Re: SDRAM debugging is not happening on imxrt1051 processor target board

venkataddagatla — Mon, 13 Jun 2022 05:47:05 GMT

Actually we want to use SDRAM and NAND on Semc bus. We had assigned the pins as mentioned in the Pin mux of the semc module. That is the reason you have seen the SEMC_ADDR08 connects to A8 pin of SDRAM and the same goes to CE# of NAND flash and all other as same as mentioned in the doc.

Is it possible by properly configuring IOCR register we can able to operate both without issues?

Kindly suggest, as we want to run our application from SDRAM and want to store data in NAND flash in runtime. Will it be an issue?

Re: SDRAM debugging is not happening on imxrt1051 processor target board

jingpan — Mon, 13 Jun 2022 09:48:27 GMT

Hi @venkataddagatla ,

No. Please change NAND CE# to other pin.

Regards,

Jing

Re: SDRAM debugging is not happening on imxrt1051 processor target board

venkataddagatla — Mon, 13 Jun 2022 13:26:30 GMT

Thanks for the response.

Do you mean only SDRAM should use that pin and remove from NAND. Can you help how we can interface both (SDRAM and NAND) on semc bus. Kindly share the example if you have any.

Re: SDRAM debugging is not happening on imxrt1051 processor target board

jingpan — Tue, 14 Jun 2022 07:07:53 GMT

Hi @venkataddagatla ,

Yes. IOCR can only be set during initialization. You can't change it frequently at run time. That doesn't make sense. But I can't find any other examples or cases like yours. Few new project use parallel NAND flash now.

Regards,

Jing