<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Understanding why we need RTS delay for RS485 communication in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-why-we-need-RTS-delay-for-RS485-communication/m-p/1466100#M190964</link>
    <description>&lt;P&gt;Any idea ?&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 30 May 2022 08:10:18 GMT</pubDate>
    <dc:creator>FabienLahoudere</dc:creator>
    <dc:date>2022-05-30T08:10:18Z</dc:date>
    <item>
      <title>Understanding why we need RTS delay for RS485 communication</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-why-we-need-RTS-delay-for-RS485-communication/m-p/1455478#M190187</link>
      <description>&lt;P&gt;On our product, RS485 communication requires to add some delays before setting RTS.&lt;/P&gt;&lt;P&gt;Without these delays, it’s not possible to repeat messages sent to a connected device, the second transmission always fails.&lt;/P&gt;&lt;P&gt;We found a patch to fix the issue but we want to understand why this delay is needed.&lt;/P&gt;&lt;P&gt;Below we summarize linux(5.4) imx uart driver.&lt;/P&gt;&lt;P&gt;The first transaction always succeed.&lt;/P&gt;&lt;P&gt;If we do not add a delay before imx_uart_transmit_buffer,&amp;nbsp;imx_uart_int never return successfully.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;EM&gt;INIT ONCE: imx_uart_rts_inactive: do mctrl_gpio_set(... 2) LEAD TO: trace_gpio_value 91 0 0 = RTS INACTIVE = RECEIVE &lt;/EM&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;EM&gt;LOOP { &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; imx_uart_start_tx &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;imx_uart_rts_active: LEAD TO: trace_gpio_value 91 0 1 = RTS ACTIVE = SEND &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;imx_uart_stop_rx &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;imx_uart_int (irq=65) USR1_TRDY||USR2_TXDC, ucr1=2040 &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp;&amp;nbsp;/*** DELAY HERE OR EARLIER (e.g. imx_uart_start_tx, even before the imx_uart_rts_active) FIXES IT ***/ &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; imx_uart_transmit_buffer send whole TX buffer (with imx_uart_writel(sport, sport-&amp;gt;port.x_char, URTX0);) &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; /*** DELAY HERE OR LATER DOES ***NOT*** FIX IT ***/ &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; &amp;nbsp;imx_uart_stop_tx &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; &amp;nbsp;imx_uart_int (irq=65) USR1_TRDY||USR2_TXDC, ucr1=0040 &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; &amp;nbsp;imx_uart_transmit_buffer uart_circ_empty &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; &amp;nbsp;imx_uart_stop_tx continued... &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; &amp;nbsp;imx_uart_rts_inactive: do mctrl_gpio_set(... 2) RTS INACTIVE = RECEIVE &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; &amp;nbsp;imx_uart_start_rx &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; imx_uart_int (irq=65) USR1_RRDY|USR1_AGTIM, usr1=0200 THERE IS NO USR1_RRDY|USR1_AGTIM IRQ IN CASE OF FAILURE &amp;lt;---- &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;&amp;nbsp; __imx_uart_rxint read whole RX buffer &lt;/EM&gt;&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;&lt;EM&gt;}&lt;/EM&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Can you help us understanding what happen and why we need this delay even before setting RTS active ?&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Tue, 10 May 2022 07:54:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Understanding-why-we-need-RTS-delay-for-RS485-communication/m-p/1455478#M190187</guid>
      <dc:creator>FabienLahoudere</dc:creator>
      <dc:date>2022-05-10T07:54:50Z</dc:date>
    </item>
    <item>
      <title>Re: Understanding why we need RTS delay for RS485 communication</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-why-we-need-RTS-delay-for-RS485-communication/m-p/1466100#M190964</link>
      <description>&lt;P&gt;Any idea ?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 30 May 2022 08:10:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Understanding-why-we-need-RTS-delay-for-RS485-communication/m-p/1466100#M190964</guid>
      <dc:creator>FabienLahoudere</dc:creator>
      <dc:date>2022-05-30T08:10:18Z</dc:date>
    </item>
    <item>
      <title>Re: Understanding why we need RTS delay for RS485 communication</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Understanding-why-we-need-RTS-delay-for-RS485-communication/m-p/1468701#M191148</link>
      <description>&lt;P&gt;It might be a limitation of the connected RS485 device.&lt;BR /&gt;You seem to be getting TXDC, so this means the transmission was OK.&lt;BR /&gt;Does it fail for other devices?&lt;BR /&gt;Does it fail at lower baud rates?&lt;/P&gt;</description>
      <pubDate>Fri, 03 Jun 2022 11:51:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Understanding-why-we-need-RTS-delay-for-RS485-communication/m-p/1468701#M191148</guid>
      <dc:creator>nvbolhuis2</dc:creator>
      <dc:date>2022-06-03T11:51:42Z</dc:date>
    </item>
  </channel>
</rss>

