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    <title>i.MX ProcessorsのトピックRT685 FIR</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/RT685-FIR/m-p/1463369#M190782</link>
    <description>&lt;P&gt;Hi all!&lt;/P&gt;&lt;P&gt;I want to make a filter for 10,000 taps for each of the 8 audio channels 48000(sample rate) on this processor. I can't find an example of a FIR filter for him.&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. How can I better store the FP32 coefficients in memory (10000taps*4byte*8cahnnels)so that the Cortex M33 is not a bottleneck in the system?&lt;/P&gt;&lt;P&gt;2.&amp;nbsp;Is there enough CPU power for such a task?&lt;/P&gt;</description>
    <pubDate>Tue, 24 May 2022 16:19:23 GMT</pubDate>
    <dc:creator>insert</dc:creator>
    <dc:date>2022-05-24T16:19:23Z</dc:date>
    <item>
      <title>RT685 FIR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT685-FIR/m-p/1463369#M190782</link>
      <description>&lt;P&gt;Hi all!&lt;/P&gt;&lt;P&gt;I want to make a filter for 10,000 taps for each of the 8 audio channels 48000(sample rate) on this processor. I can't find an example of a FIR filter for him.&amp;nbsp;&lt;/P&gt;&lt;P&gt;1. How can I better store the FP32 coefficients in memory (10000taps*4byte*8cahnnels)so that the Cortex M33 is not a bottleneck in the system?&lt;/P&gt;&lt;P&gt;2.&amp;nbsp;Is there enough CPU power for such a task?&lt;/P&gt;</description>
      <pubDate>Tue, 24 May 2022 16:19:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT685-FIR/m-p/1463369#M190782</guid>
      <dc:creator>insert</dc:creator>
      <dc:date>2022-05-24T16:19:23Z</dc:date>
    </item>
    <item>
      <title>Re: RT685 FIR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/RT685-FIR/m-p/1465412#M190897</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt600-crossover-mcu-with-arm-cortex-m33-and-dsp-cores:i.MX-RT600" target="_self"&gt;RT600&lt;/A&gt; is c&lt;SPAN&gt;ombining a high-performance Cadence&lt;/SPAN&gt;&lt;SUP&gt;®&lt;/SUP&gt;&lt;SPAN&gt;&amp;nbsp;Tensilica&lt;/SPAN&gt;&lt;SUP&gt;®&amp;nbsp;&lt;A href="https://www.cadence.com/en_US/home/company/newsroom/press-releases/pr/2015/cadence-announces-fourth-generation-tensilica-hifi-dsp-architecture.html" target="_self"&gt;HiFi 4 audio DSP core&lt;/A&gt;&amp;nbsp;&lt;/SUP&gt;&lt;SPAN&gt;.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;DSP core has advantage for data processsing vs. ARM Cortex-M33 core, which includes&amp;nbsp;finite impulse response (FIR).&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;I would recommend customer to refer and download Cadence HIFI DSP software development toolchain from &lt;A href="https://tensilicatools.com/platform/i-mx-rt600/" target="_self"&gt;here&lt;/A&gt;.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Wish it helps.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Mike&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 27 May 2022 08:04:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/RT685-FIR/m-p/1465412#M190897</guid>
      <dc:creator>Hui_Ma</dc:creator>
      <dc:date>2022-05-27T08:04:44Z</dc:date>
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