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    <title>topic Re: QSPI MIMXRT1051CVL5B in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1459086#M190444</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200625"&gt;@sapirbuz&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;If you use both your mentioned QSPI pin to the same flexSPI port, then you can't, please check the flexSPI port pin related information:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="kerryzhou_0-1652770125026.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/179972iEBB8BC273E51F7BC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="kerryzhou_0-1652770125026.png" alt="kerryzhou_0-1652770125026.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;This one boot and XIP are OK:&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;QSPI for boot (pins G&lt;/SPAN&gt;&lt;SPAN class=""&gt;PIO_SD_B1_05,&amp;nbsp;GPIO_SD_B1_06,&amp;nbsp;GPIO_SD_B1_00,&amp;nbsp;GPIO_SD_B1_07,&amp;nbsp;GPIO_SD_B1_08,&amp;nbsp;GPIO_SD_B1_09,&amp;nbsp;GPIO_SD_B1_10 and GPIO_SD_B1_11) ALT 1, ALT6 for SS1&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;But if your code is running in the above flexSPI A port, then you can't connect other QSPI flash to the same flexSPI port, altough they are the different pins.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;But your mentioned pins:&amp;nbsp;&lt;SPAN&gt;pins&amp;nbsp;&lt;/SPAN&gt;GPIO_AD_B1_08,&amp;nbsp; GPIO_AD_B1_09,&amp;nbsp; GPIO_AD_B1_10,&amp;nbsp; GPIO_AD_B1_11,&amp;nbsp; GPIO_AD_B1_12 ,&amp;nbsp; GPIO_AD_B1_13,&amp;nbsp; GPIO_AD_B1_14 and&amp;nbsp; GPIO_AD_B1_15&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Can be used to other function.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;So, summarize it,&amp;nbsp; two QSPI flash chip, which you mentioned, even it is the different pins, but it is the same flexSPI port.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Just one way, your first one QSPI flash just for booting, then you copy all the code to the internal RAM, and run it in internal RAM, then, you can check the flexSPI pins to another pin, and do the communicate with the second group QSPI flash, and make sure all the code is in the internal RAM, not the boot flash.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Wish it helps you!&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Kerry&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Tue, 17 May 2022 06:53:06 GMT</pubDate>
    <dc:creator>kerryzhou</dc:creator>
    <dc:date>2022-05-17T06:53:06Z</dc:date>
    <item>
      <title>QSPI MIMXRT1051CVL5B</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1458813#M190429</link>
      <description>&lt;P&gt;Can we use QSPI for boot (pins G&lt;SPAN class=""&gt;PIO_SD_B1_05,&amp;nbsp;GPIO_SD_B1_06,&amp;nbsp;GPIO_SD_B1_00,&amp;nbsp;GPIO_SD_B1_07,&amp;nbsp;GPIO_SD_B1_08,&amp;nbsp;GPIO_SD_B1_09,&amp;nbsp;GPIO_SD_B1_10 and GPIO_SD_B1_11) ALT 1, ALT6 for SS1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;and another QSPI for another usage? (pins&amp;nbsp;&lt;SPAN class=""&gt;GPIO_AD_B1_08,&amp;nbsp; GPIO_AD_B1_09,&amp;nbsp; GPIO_AD_B1_10,&amp;nbsp; GPIO_AD_B1_11,&amp;nbsp; GPIO_AD_B1_12 ,&amp;nbsp; GPIO_AD_B1_13,&amp;nbsp; GPIO_AD_B1_14 and&amp;nbsp; GPIO_AD_B1_15)- ALT 0&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 16 May 2022 18:41:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1458813#M190429</guid>
      <dc:creator>sapirbuz</dc:creator>
      <dc:date>2022-05-16T18:41:57Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI MIMXRT1051CVL5B</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1459086#M190444</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200625"&gt;@sapirbuz&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; &amp;nbsp;If you use both your mentioned QSPI pin to the same flexSPI port, then you can't, please check the flexSPI port pin related information:&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="kerryzhou_0-1652770125026.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/179972iEBB8BC273E51F7BC/image-size/medium?v=v2&amp;amp;px=400" role="button" title="kerryzhou_0-1652770125026.png" alt="kerryzhou_0-1652770125026.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;This one boot and XIP are OK:&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;QSPI for boot (pins G&lt;/SPAN&gt;&lt;SPAN class=""&gt;PIO_SD_B1_05,&amp;nbsp;GPIO_SD_B1_06,&amp;nbsp;GPIO_SD_B1_00,&amp;nbsp;GPIO_SD_B1_07,&amp;nbsp;GPIO_SD_B1_08,&amp;nbsp;GPIO_SD_B1_09,&amp;nbsp;GPIO_SD_B1_10 and GPIO_SD_B1_11) ALT 1, ALT6 for SS1&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;But if your code is running in the above flexSPI A port, then you can't connect other QSPI flash to the same flexSPI port, altough they are the different pins.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;But your mentioned pins:&amp;nbsp;&lt;SPAN&gt;pins&amp;nbsp;&lt;/SPAN&gt;GPIO_AD_B1_08,&amp;nbsp; GPIO_AD_B1_09,&amp;nbsp; GPIO_AD_B1_10,&amp;nbsp; GPIO_AD_B1_11,&amp;nbsp; GPIO_AD_B1_12 ,&amp;nbsp; GPIO_AD_B1_13,&amp;nbsp; GPIO_AD_B1_14 and&amp;nbsp; GPIO_AD_B1_15&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Can be used to other function.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;So, summarize it,&amp;nbsp; two QSPI flash chip, which you mentioned, even it is the different pins, but it is the same flexSPI port.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Just one way, your first one QSPI flash just for booting, then you copy all the code to the internal RAM, and run it in internal RAM, then, you can check the flexSPI pins to another pin, and do the communicate with the second group QSPI flash, and make sure all the code is in the internal RAM, not the boot flash.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Wish it helps you!&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN class=""&gt;Kerry&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 17 May 2022 06:53:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1459086#M190444</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-05-17T06:53:06Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI MIMXRT1051CVL5B</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1463047#M190751</link>
      <description>&lt;P&gt;Thank you &lt;LI-EMOJI id="lia_slightly-smiling-face" title=":slightly_smiling_face:"&gt;&lt;/LI-EMOJI&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 24 May 2022 08:27:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1463047#M190751</guid>
      <dc:creator>sapirbuz</dc:creator>
      <dc:date>2022-05-24T08:27:09Z</dc:date>
    </item>
    <item>
      <title>Re: QSPI MIMXRT1051CVL5B</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1463159#M190767</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/200625"&gt;@sapirbuz&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp; You are welcome!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;If your question is solved, please help to mark the correct answer just to close this case, any new issues, welcome to create the new question post, thanks.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;
&lt;P&gt;Kerry&lt;/P&gt;</description>
      <pubDate>Tue, 24 May 2022 10:30:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/QSPI-MIMXRT1051CVL5B/m-p/1463159#M190767</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2022-05-24T10:30:25Z</dc:date>
    </item>
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