i.MX ProcessorsのトピックRe: iMX6Q - Capturing two MIPI-CSI camera streams

iMX6Q - Capturing two MIPI-CSI camera streams

martin_lovric — Mon, 16 May 2022 10:00:31 GMT

Hello,

I'm trying to enable two MIPI-CSI video streams on iMX6Q. Diagram bellow shows the HW setup.

Since we're using newer BSP version (4.1.15), I've ported changes from patches included here:
https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/iMX6DQ-MAX9286-MIPI-CSI2-720P-camera-surround-view-solution-for/ta-p/1116501.

The stream from VC1 (/dev/video1) is visible with some artifacts appearing on screen, but the stream from VC0 (/dev/video0) is not.

Does anyone have an idea how to debug this issue to determine in which segment of the pipeline is the stream stuck and why? Is it the Camera hub, MIPI-CSI2 receiver, CSI2IPU gasket, IPU1 mux, etc...

Additional info:
Baseboard: Custom
SoM: Toradex Apalis iMX6Q
OS: Yocto based custom Linux
Kernel version: 4.14.117

BR!
Martin Lovrić

Re: iMX6Q - Capturing two MIPI-CSI camera streams

martin_lovric — Mon, 16 May 2022 13:10:46 GMT

I managed to get second stream working by avoiding IPU MUX elements, instead of VC0 I used VC2, the problem remains why VC0 doesn't work.

FYI: In driver I have enabled CSI input for IPU1 mux:

regmap_update_bits(gpr, IOMUXC_GPR1, 3 << 19, 0 << 19);

Re: iMX6Q - Capturing two MIPI-CSI camera streams

joanxie — Thu, 19 May 2022 06:19:26 GMT

" instead of VC0 I used VC2"

>is it your typo? do you mean change VC1 to VC2, not VC0, right? pls check the debug document for imx6 mipi camera

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/Debug-steps-for-customer-MIPI-sensor-docx/ta-p/1120244

Re: iMX6Q - Capturing two MIPI-CSI camera streams

martin_lovric — Fri, 20 May 2022 08:38:40 GMT

"is it your typo?"

No. I've attached the pictures which explain the situation

"pls check the debug document for imx6 mipi camera"
thank you for the doc, I'll take a look at it