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    <title>i.MX Processors中的主题 DMA transfer peripheral type</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/DMA-transfer-peripheral-type/m-p/1458289#M190381</link>
    <description>&lt;P&gt;Hello community, I am working on imx8mm.&lt;BR /&gt;Is this DTS correct when using SAI?&lt;/P&gt;&lt;LI-CODE lang="c"&gt;sai3: sai@30030000 {
#sound-dai-cells = &amp;lt;0&amp;gt;;
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
reg = &amp;lt;0x30030000 0x10000&amp;gt;;
interrupts = &amp;lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&amp;gt;;
clocks = &amp;lt;&amp;amp;clk IMX8MM_CLK_SAI3_IPG&amp;gt;,
&amp;lt;&amp;amp;clk IMX8MM_CLK_SAI3_ROOT&amp;gt;,
&amp;lt;&amp;amp;clk IMX8MM_CLK_DUMMY&amp;gt;, &amp;lt;&amp;amp;clk IMX8MM_CLK_DUMMY&amp;gt;;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dmas = &amp;lt;&amp;amp;sdma2 4 2 0&amp;gt;, &amp;lt;&amp;amp;sdma2 5 2 0&amp;gt;;
dma-names = "rx", "tx";
status = "disabled";
};&lt;/LI-CODE&gt;&lt;P&gt;&lt;BR /&gt;In this configuration, the DMA transfer peripheral type is 2.&lt;BR /&gt;According to Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt, 2 is MMC and SAI is 24.&lt;/P&gt;&lt;P&gt;Should I fix it to 24?&lt;/P&gt;</description>
    <pubDate>Mon, 16 May 2022 01:45:23 GMT</pubDate>
    <dc:creator>kagawa</dc:creator>
    <dc:date>2022-05-16T01:45:23Z</dc:date>
    <item>
      <title>DMA transfer peripheral type</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DMA-transfer-peripheral-type/m-p/1458289#M190381</link>
      <description>&lt;P&gt;Hello community, I am working on imx8mm.&lt;BR /&gt;Is this DTS correct when using SAI?&lt;/P&gt;&lt;LI-CODE lang="c"&gt;sai3: sai@30030000 {
#sound-dai-cells = &amp;lt;0&amp;gt;;
compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
reg = &amp;lt;0x30030000 0x10000&amp;gt;;
interrupts = &amp;lt;GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH&amp;gt;;
clocks = &amp;lt;&amp;amp;clk IMX8MM_CLK_SAI3_IPG&amp;gt;,
&amp;lt;&amp;amp;clk IMX8MM_CLK_SAI3_ROOT&amp;gt;,
&amp;lt;&amp;amp;clk IMX8MM_CLK_DUMMY&amp;gt;, &amp;lt;&amp;amp;clk IMX8MM_CLK_DUMMY&amp;gt;;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dmas = &amp;lt;&amp;amp;sdma2 4 2 0&amp;gt;, &amp;lt;&amp;amp;sdma2 5 2 0&amp;gt;;
dma-names = "rx", "tx";
status = "disabled";
};&lt;/LI-CODE&gt;&lt;P&gt;&lt;BR /&gt;In this configuration, the DMA transfer peripheral type is 2.&lt;BR /&gt;According to Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt, 2 is MMC and SAI is 24.&lt;/P&gt;&lt;P&gt;Should I fix it to 24?&lt;/P&gt;</description>
      <pubDate>Mon, 16 May 2022 01:45:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DMA-transfer-peripheral-type/m-p/1458289#M190381</guid>
      <dc:creator>kagawa</dc:creator>
      <dc:date>2022-05-16T01:45:23Z</dc:date>
    </item>
    <item>
      <title>Re: DMA transfer peripheral type</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/DMA-transfer-peripheral-type/m-p/1720652#M212394</link>
      <description>&lt;P&gt;Would love to see an NXP expert answer this, or provide educational resources on this topic.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 12 Sep 2023 00:06:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/DMA-transfer-peripheral-type/m-p/1720652#M212394</guid>
      <dc:creator>tloan</dc:creator>
      <dc:date>2023-09-12T00:06:17Z</dc:date>
    </item>
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