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    <title>i.MX ProcessorsのトピックSNVS initialization issue</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SNVS-initialization-issue/m-p/1457060#M190303</link>
    <description>&lt;P&gt;I am currently developping a product based on the IM.X RT 106x devices (more specifically on a 1062) and using a BSP package running on the IMX RT 1060 EVKB board from Emcraft as the base for our design.&lt;/P&gt;&lt;P&gt;The current design step I am involved in involves using the SNVS module to store / securely access a master key from the DCP module.&lt;/P&gt;&lt;P&gt;My current issue concerns the proper initialization of the SNVS module.&lt;/P&gt;&lt;P&gt;As I am not the one having written all initialization steps in U-boot, I am currently facing an issue where it seems that I am stumbling on a SNVS device that has already been initialized and where the HP part is stuck in a "NON-SECURE" state because the SW_SV bit of the HPCOMR has been set to 1. However, while searching in the u-boot code compiled for the board I do not seem to be able to find the part of the code that would execute such an initialization.&lt;/P&gt;&lt;P&gt;I therefore am wondering whether inproper IOMUXC, PMU, GPC or CCM register settings might put the module in such a state and, if yes, what are those that I should be checking in order to evaluate this?&lt;/P&gt;&lt;P&gt;It is to be noted that the Real Time Clock provided by the block seems to be working ok.&lt;/P&gt;&lt;P&gt;As a piece of information, here is the current state of the SNVS I can get reading the different registers:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;400d4000: 00000000 80002100 00000000 00000000 .....!..........&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;HPCOMR 80002100 (NPSWA_EN=1, PROGZMK=1, SW_SV=1)&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;400d4010: 00000000 80009b00 80002000 00000000 ......... ......&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;HPSR: 80009b00 (ZMK_ZERO=1, SYS_SECURE_BOOT=1, SYS_SECURITY_CFG = 001 - open cfg)&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;HPSVSR: 80002000 (LP_SEC_VIO=1, after LP POR, I initialized the LPLVDR register at adress 0x400D4064 and ordered a reset of the LP part but this bit does not seem to be cleared, even after HP POR, SW_SV is asserted)&lt;/FONT&gt;&lt;BR /&gt;400d4020: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d4030: 00000000 00000000 00000020 00000000 ........ .......&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;LPCR : 00000020 DP_EN set to 1 (reset value)&lt;/FONT&gt;&lt;BR /&gt;400d4040: 00000000 00000000 00000000 00000008 ................&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;LPSR 00000008: LVD is set to 1 and does not reset after HP POR&lt;/FONT&gt;&lt;BR /&gt;400d4050: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d4060: 00000000 41736166 00000000 00000000&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;LPLVDR: 41736166 default value written to register to detect LP Voltage drop&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;400d4070: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d4080: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d4090: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40a0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40b0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40c0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40d0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40e0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40f0: 00000000 00000000 00000000 00000000 ................&lt;/P&gt;</description>
    <pubDate>Thu, 12 May 2022 08:00:10 GMT</pubDate>
    <dc:creator>FMA</dc:creator>
    <dc:date>2022-05-12T08:00:10Z</dc:date>
    <item>
      <title>SNVS initialization issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SNVS-initialization-issue/m-p/1457060#M190303</link>
      <description>&lt;P&gt;I am currently developping a product based on the IM.X RT 106x devices (more specifically on a 1062) and using a BSP package running on the IMX RT 1060 EVKB board from Emcraft as the base for our design.&lt;/P&gt;&lt;P&gt;The current design step I am involved in involves using the SNVS module to store / securely access a master key from the DCP module.&lt;/P&gt;&lt;P&gt;My current issue concerns the proper initialization of the SNVS module.&lt;/P&gt;&lt;P&gt;As I am not the one having written all initialization steps in U-boot, I am currently facing an issue where it seems that I am stumbling on a SNVS device that has already been initialized and where the HP part is stuck in a "NON-SECURE" state because the SW_SV bit of the HPCOMR has been set to 1. However, while searching in the u-boot code compiled for the board I do not seem to be able to find the part of the code that would execute such an initialization.&lt;/P&gt;&lt;P&gt;I therefore am wondering whether inproper IOMUXC, PMU, GPC or CCM register settings might put the module in such a state and, if yes, what are those that I should be checking in order to evaluate this?&lt;/P&gt;&lt;P&gt;It is to be noted that the Real Time Clock provided by the block seems to be working ok.&lt;/P&gt;&lt;P&gt;As a piece of information, here is the current state of the SNVS I can get reading the different registers:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;400d4000: 00000000 80002100 00000000 00000000 .....!..........&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;HPCOMR 80002100 (NPSWA_EN=1, PROGZMK=1, SW_SV=1)&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;400d4010: 00000000 80009b00 80002000 00000000 ......... ......&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;HPSR: 80009b00 (ZMK_ZERO=1, SYS_SECURE_BOOT=1, SYS_SECURITY_CFG = 001 - open cfg)&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;HPSVSR: 80002000 (LP_SEC_VIO=1, after LP POR, I initialized the LPLVDR register at adress 0x400D4064 and ordered a reset of the LP part but this bit does not seem to be cleared, even after HP POR, SW_SV is asserted)&lt;/FONT&gt;&lt;BR /&gt;400d4020: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d4030: 00000000 00000000 00000020 00000000 ........ .......&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;LPCR : 00000020 DP_EN set to 1 (reset value)&lt;/FONT&gt;&lt;BR /&gt;400d4040: 00000000 00000000 00000000 00000008 ................&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;LPSR 00000008: LVD is set to 1 and does not reset after HP POR&lt;/FONT&gt;&lt;BR /&gt;400d4050: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d4060: 00000000 41736166 00000000 00000000&lt;/P&gt;&lt;P&gt;&lt;FONT color="#00FF00"&gt;LPLVDR: 41736166 default value written to register to detect LP Voltage drop&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;400d4070: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d4080: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d4090: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40a0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40b0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40c0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40d0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40e0: 00000000 00000000 00000000 00000000 ................&lt;BR /&gt;400d40f0: 00000000 00000000 00000000 00000000 ................&lt;/P&gt;</description>
      <pubDate>Thu, 12 May 2022 08:00:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SNVS-initialization-issue/m-p/1457060#M190303</guid>
      <dc:creator>FMA</dc:creator>
      <dc:date>2022-05-12T08:00:10Z</dc:date>
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