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    <title>topic IMX8MM DDR validation test with Config Tools V11 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1447455#M189566</link>
    <description>&lt;P&gt;I am trying to use Config Tools V11 to run some DDR test.&amp;nbsp; I loaded in my .DS file for DDR3L memory and verified the pmic and UART commands are in ddr_config.ds.&amp;nbsp; I added them into Advanced mode &amp;gt; Board config as well.&amp;nbsp; The Processor we are using is MIMX8MM5DVTLZ.&amp;nbsp;&lt;/P&gt;&lt;P&gt;After selecting the COM I try to run any of the test and get the following error.&lt;/P&gt;&lt;P&gt;INFO memtool.phyinit.phy_init Run phyinit for 2017.09\ddr3&lt;BR /&gt;[Error]// [dwc_ddrphy_phyinit_setUserInput] unknown PhyInit field name 'Lp4RxPreambleMode[0]'&lt;/P&gt;</description>
    <pubDate>Thu, 21 Apr 2022 20:44:45 GMT</pubDate>
    <dc:creator>slira</dc:creator>
    <dc:date>2022-04-21T20:44:45Z</dc:date>
    <item>
      <title>IMX8MM DDR validation test with Config Tools V11</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1447455#M189566</link>
      <description>&lt;P&gt;I am trying to use Config Tools V11 to run some DDR test.&amp;nbsp; I loaded in my .DS file for DDR3L memory and verified the pmic and UART commands are in ddr_config.ds.&amp;nbsp; I added them into Advanced mode &amp;gt; Board config as well.&amp;nbsp; The Processor we are using is MIMX8MM5DVTLZ.&amp;nbsp;&lt;/P&gt;&lt;P&gt;After selecting the COM I try to run any of the test and get the following error.&lt;/P&gt;&lt;P&gt;INFO memtool.phyinit.phy_init Run phyinit for 2017.09\ddr3&lt;BR /&gt;[Error]// [dwc_ddrphy_phyinit_setUserInput] unknown PhyInit field name 'Lp4RxPreambleMode[0]'&lt;/P&gt;</description>
      <pubDate>Thu, 21 Apr 2022 20:44:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1447455#M189566</guid>
      <dc:creator>slira</dc:creator>
      <dc:date>2022-04-21T20:44:45Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MM DDR validation test with Config Tools V11</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1447607#M189572</link>
      <description>&lt;P&gt;You can refer to &lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 22 Apr 2022 05:32:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1447607#M189572</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2022-04-22T05:32:25Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MM DDR validation test with Config Tools V11</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1447920#M189590</link>
      <description>&lt;P&gt;I have referred to the page you have mentioned and have tried to use the standalone DDR tool but can't seem to find the correct settings.&amp;nbsp; I was to try to use Config tools to see if maybe it would give me little more insight as to what is going on.&amp;nbsp; This is the end of the log file where the error happens.&lt;/P&gt;&lt;P&gt;DEBUG memtool.common.factories new instance -&amp;gt; &amp;lt;memtool.processor.imx8m.mimx8mm.MIMX8MM object at 0x00000275A788FA00&amp;gt;&lt;BR /&gt;DEBUG memtool.common.factories new instance -&amp;gt; &amp;lt;memtool.processor.imx8m.mimx8mm.MIMX8MM object at 0x00000275A788FA30&amp;gt;&lt;BR /&gt;INFO memtool.phyinit.phy_init Run phyinit for 2017.09\ddr3&lt;BR /&gt;DEBUG memtool.phyinit.phy_init Shared library C:\ProgramData\NXP\mcu_data_v11\processors\MIMX8MM5xxxLZ\ksdk2_0\mem_validation\ddrc\phyinit\sharedlib\phyinit_2017.09_ddr3.dll&lt;BR /&gt;DEBUG memtool.common.factories new instance -&amp;gt; &amp;lt;memtool.phyinit.phy_init.PHYInitDriver object at 0x00000275A78C3460&amp;gt;&lt;BR /&gt;DEBUG memtool.phyinit.phy_init PHY config file C:\Users\slira\AppData\Local\Temp\mem_validation\phy_config_final.json&lt;BR /&gt;DEBUG memtool.phyinit.phy_init Phyinit output file C:\Users\slira\AppData\Local\Temp\mem_validation\phy_training_out_1d2d.txt&lt;BR /&gt;[Error]// [dwc_ddrphy_phyinit_setUserInput] unknown PhyInit field name 'Lp4RxPreambleMode[0]'&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am not sure what setting is tied to&amp;nbsp;'Lp4RxPreambleMode[0]'&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If this is tied to the memory, we are using ISSI part #&amp;nbsp;IS43TR16K01S2AL-125KBL.&lt;/P&gt;&lt;P&gt;Datasheet for ISSI part:&amp;nbsp;&lt;A href="https://www.issi.com/WW/pdf/43-46TR16K01S2A-AL.pdf" target="_blank"&gt;https://www.issi.com/WW/pdf/43-46TR16K01S2A-AL.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;These are the settings I am using for this part.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="slira_0-1650641527567.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177759iD8E3F7FD268DEF20/image-size/medium?v=v2&amp;amp;px=400" role="button" title="slira_0-1650641527567.png" alt="slira_0-1650641527567.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;When I run the test I different results in Step 2: DDR memory accessing. This is a sample of one of the runs.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="slira_1-1650641664313.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177760i96D95DA7C678325D/image-size/medium?v=v2&amp;amp;px=400" role="button" title="slira_1-1650641664313.png" alt="slira_1-1650641664313.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;The address of failure can change on different runs as well as the both patterns.&lt;/P&gt;&lt;P&gt;Any insight would be much appreciated.&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 22 Apr 2022 15:36:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1447920#M189590</guid>
      <dc:creator>slira</dc:creator>
      <dc:date>2022-04-22T15:36:00Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MM DDR validation test with Config Tools V11</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1448013#M189592</link>
      <description>&lt;P&gt;I have been running some more test and came across a post that is very similar to ours but it was using ddr4 memory where we are using ddr3 memory. They are also running a Nano where as we are using a MIMX8MM5DVTLZAA. We are also running a dual-die memory chip.&lt;/P&gt;&lt;P&gt;&amp;nbsp; The post is:&amp;nbsp;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/How-to-calibrate-DDR4-on-i-MX8M-nano-with-i-MX-Mscale-DDR-Tool/m-p/1024793" target="_blank" rel="noopener"&gt;https://community.nxp.com/t5/i-MX-Processors/How-to-calibrate-DDR4-on-i-MX8M-nano-with-i-MX-Mscale-DDR-Tool/m-p/1024793&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have it down to where I am running into 1 bit being off consistently.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="slira_0-1650665459071.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177778i8F48256DDF50A30F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="slira_0-1650665459071.png" alt="slira_0-1650665459071.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Manually reading the address shows everything in the 0x400800000 address doesn't get the bit set.&amp;nbsp; Please see below.&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="slira_1-1650665580107.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/177779iBFA6997663AE0E73/image-size/medium?v=v2&amp;amp;px=400" role="button" title="slira_1-1650665580107.png" alt="slira_1-1650665580107.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 22 Apr 2022 22:15:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR-validation-test-with-Config-Tools-V11/m-p/1448013#M189592</guid>
      <dc:creator>slira</dc:creator>
      <dc:date>2022-04-22T22:15:32Z</dc:date>
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