https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-Transfer-Delay/m-p/1444694#M189386 <P>Hello,</P><P>Does anyone know what causes the ~200ns clock delays between words in a dma spi transfer?</P><P>Does it have to do with the latency with of wait_for_completion_timeout for rx/tx in</P><P>spi_imx_dma_transfer?</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="marcuscastlepeakinc_0-1650065212203.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/177089i8EB6BD310DAAE62F/image-size/medium?v=v2&amp;px=400" role="button" title="marcuscastlepeakinc_0-1650065212203.png" alt="marcuscastlepeakinc_0-1650065212203.png" /></span></P><P>Thanks!</P> Fri, 15 Apr 2022 23:27:39 GMT marcus-castlepeakinc 2022-04-15T23:27:39Z https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-Transfer-Delay/m-p/1444694#M189386 <P>Hello,</P><P>Does anyone know what causes the ~200ns clock delays between words in a dma spi transfer?</P><P>Does it have to do with the latency with of wait_for_completion_timeout for rx/tx in</P><P>spi_imx_dma_transfer?</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="marcuscastlepeakinc_0-1650065212203.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/177089i8EB6BD310DAAE62F/image-size/medium?v=v2&amp;px=400" role="button" title="marcuscastlepeakinc_0-1650065212203.png" alt="marcuscastlepeakinc_0-1650065212203.png" /></span></P><P>Thanks!</P> Fri, 15 Apr 2022 23:27:39 GMT https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-Transfer-Delay/m-p/1444694#M189386 marcus-castlepeakinc 2022-04-15T23:27:39Z https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-Transfer-Delay/m-p/1453476#M190026 <P>This is caused by spi driver doing separate 8 bit transfers (ECSPIx_CONREG . BURST_LENGHT = <LI-EMOJI id="lia_smiling-face-with-sunglasses" title=":smiling_face_with_sunglasses:"></LI-EMOJI> instead of doing single transfer with BURST_LENGTH set to total transfer bit count.&nbsp;For the same reason hardware chip select is of no use, forcing nearly everyone to use software toggled CS.</P> Thu, 05 May 2022 11:30:12 GMT https://community.nxp.com/t5/i-MX-Processors/SPI-DMA-Transfer-Delay/m-p/1453476#M190026 kef2 2022-05-05T11:30:12Z