https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR4-Configuration-in-U-Boot/m-p/1441918#M189146 <P>Hi Team,</P><P>below is the sequence we have followed for DDDR changes.</P><P>1.Please find the attached RPA and .ds file used for DDR4 programming<BR />2.Performed Mscale DDR4 stress test and collected generated ddr_timing.c<BR />3.Replaced existing ddr_timing.c with the latest one in uboot at path: vendor/nxp-opensource/uboot-imx/board/freescale/imx8mm_evk<BR />4.compiled the source code and flashed binaries with both UUU and SD card.</P><P>below are the failure UART logs observed on Tera term<BR /><BR />By default IMX8MM EVK supports LPDDR4, but our custom board has DDR4 with 4GB density.<BR />could you please confirm are we missing anything in DDR4 configuration in uboot.</P><P>Thanks,</P><P>Raghavendra</P> Mon, 11 Apr 2022 08:13:04 GMT Raghavendra 2022-04-11T08:13:04Z https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR4-Configuration-in-U-Boot/m-p/1441918#M189146 <P>Hi Team,</P><P>below is the sequence we have followed for DDDR changes.</P><P>1.Please find the attached RPA and .ds file used for DDR4 programming<BR />2.Performed Mscale DDR4 stress test and collected generated ddr_timing.c<BR />3.Replaced existing ddr_timing.c with the latest one in uboot at path: vendor/nxp-opensource/uboot-imx/board/freescale/imx8mm_evk<BR />4.compiled the source code and flashed binaries with both UUU and SD card.</P><P>below are the failure UART logs observed on Tera term<BR /><BR />By default IMX8MM EVK supports LPDDR4, but our custom board has DDR4 with 4GB density.<BR />could you please confirm are we missing anything in DDR4 configuration in uboot.</P><P>Thanks,</P><P>Raghavendra</P> Mon, 11 Apr 2022 08:13:04 GMT https://community.nxp.com/t5/i-MX-Processors/IMX8MM-DDR4-Configuration-in-U-Boot/m-p/1441918#M189146 Raghavendra 2022-04-11T08:13:04Z