<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
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    <title>topic Re: iMX8M Mini: PCI with CSI problem in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1436011#M188774</link>
    <description>&lt;P&gt;Just to add to Kamil's message, there is a problem with CSI interrupts during PCIe communication. We set pin high at the beginning of&amp;nbsp;&lt;SPAN&gt;mx6s_csi_irq_handler and low at the end.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot 2022-03-30 at 10.37.56.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/175270i5B2417CF5DE0F5AD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2022-03-30 at 10.37.56.png" alt="Screenshot 2022-03-30 at 10.37.56.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Without PCIe communication we get 120 irq/sec with about 8 ms between each interrupt, as soon as we start PCIe communication delays between two interrupts may be 16+ ms which makes a problem with CSI reception and RX fifo overflows.&lt;/P&gt;&lt;P&gt;Is it possible to set PCIe interrupts to a lower priority so the CSI triggers in time?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;Krzysztof&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 30 Mar 2022 08:47:27 GMT</pubDate>
    <dc:creator>td-krzysiek</dc:creator>
    <dc:date>2022-03-30T08:47:27Z</dc:date>
    <item>
      <title>iMX8M Mini: PCI with CSI problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1434077#M188629</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;We are using iMX8M mini (5.4.47 kernel) with a camera (1080p 60fps) via CSI and a device on PCI.&lt;BR /&gt;We collect the data and encode on the board. When we are trying to run anything on PCI interface it causes error from&amp;nbsp;from&amp;nbsp;mx6s_capture.c (1107 line)&lt;/P&gt;&lt;PRE&gt;&lt;SPAN class=""&gt;Rx fifo overflow&lt;/SPAN&gt;&lt;/PRE&gt;&lt;P&gt;We aren't able to use both camera and PCI device at once because of that issue.&lt;BR /&gt;It looks like we have got some collision between those peripherals, but we didn't see any issue with PCI drivers. The problem occurs only on CSI interface.&lt;/P&gt;&lt;P&gt;How to find out the root of that problem? We were checking logs from DMA and interrupts and didn't notice any suspicious behavior. It looks like the system cannot handle those two communications at once.&lt;/P&gt;</description>
      <pubDate>Fri, 25 Mar 2022 09:45:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1434077#M188629</guid>
      <dc:creator>TDKamil</dc:creator>
      <dc:date>2022-03-25T09:45:51Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8M Mini: PCI with CSI problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1436011#M188774</link>
      <description>&lt;P&gt;Just to add to Kamil's message, there is a problem with CSI interrupts during PCIe communication. We set pin high at the beginning of&amp;nbsp;&lt;SPAN&gt;mx6s_csi_irq_handler and low at the end.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot 2022-03-30 at 10.37.56.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/175270i5B2417CF5DE0F5AD/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2022-03-30 at 10.37.56.png" alt="Screenshot 2022-03-30 at 10.37.56.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Without PCIe communication we get 120 irq/sec with about 8 ms between each interrupt, as soon as we start PCIe communication delays between two interrupts may be 16+ ms which makes a problem with CSI reception and RX fifo overflows.&lt;/P&gt;&lt;P&gt;Is it possible to set PCIe interrupts to a lower priority so the CSI triggers in time?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind regards,&lt;/P&gt;&lt;P&gt;Krzysztof&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 30 Mar 2022 08:47:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1436011#M188774</guid>
      <dc:creator>td-krzysiek</dc:creator>
      <dc:date>2022-03-30T08:47:27Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8M Mini: PCI with CSI problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1438513#M188943</link>
      <description>&lt;P&gt;Just to add to it, here is output from mx6s_log_counters function:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;```&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.480663&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;At least 1 datum (word) is ready in RXFIFO events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;1603&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.486926&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;Error is detected in CCIR coding events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.492060&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;Hresponse error is detected events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.496762&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;Change of video field is detected events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.501982&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;Field 1 of video is about to start events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;2916&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.507550&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;Field 2 of video is about to start events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.512859&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;SOF is detected events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;1494&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.516777&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;EOF is detected events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;1337&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.520697&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;RXFIFO Full Interrupt Status events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;163&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.525658&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;DMA Transfer Done in Frame Buffer1 events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;616&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.531140&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;DMA Transfer Done in Frame Buffer2 events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;597&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.536623&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;STATFIFO Full Interrupt Status events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;1934&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.541846&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;DMA Transfer Done from StatFIFO events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;0&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.546892&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;RXFIFO has overflowed events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;212&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.551245&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;STATFIFO has overflowed events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;1312&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.555858&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;DMA field 1 is complete events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;1253&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.560471&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;DMA field 0 is complete events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;1253&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;[ &lt;/SPAN&gt;&lt;SPAN&gt;4362.565084&lt;/SPAN&gt;&lt;SPAN&gt;] &lt;/SPAN&gt;&lt;SPAN&gt;Base address switching occur before DMA complete events&lt;/SPAN&gt;&lt;SPAN&gt;: &lt;/SPAN&gt;&lt;SPAN&gt;140&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;```&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 04 Apr 2022 19:01:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1438513#M188943</guid>
      <dc:creator>td-krzysiek</dc:creator>
      <dc:date>2022-04-04T19:01:18Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8M Mini: PCI with CSI problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1441579#M189122</link>
      <description>&lt;P&gt;It seems that RX FIFO Full always occurs after 7th PCI MSI interrupt, RX FIFO Full precedes ADDR_CH_ERR_INT.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Screenshot 2022-04-09 at 10.39.26.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/176424i8FDE8312619D0F1A/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Screenshot 2022-04-09 at 10.39.26.png" alt="Screenshot 2022-04-09 at 10.39.26.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Sat, 09 Apr 2022 08:43:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-PCI-with-CSI-problem/m-p/1441579#M189122</guid>
      <dc:creator>td-krzysiek</dc:creator>
      <dc:date>2022-04-09T08:43:06Z</dc:date>
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  </channel>
</rss>

