https://community.nxp.com/t5/i-MX-Processors/i-MX7-HAB-SEC-CONFIG-bits-all-read-zero/m-p/1434984#M188693 <P>Greetings. I have been trying to learn how to configure HAB on an i.MX7 and have came across a confusing observation regarding the SEC_CONFIG bits.&nbsp;&nbsp;<BR />The reference manual describes the SEC_CONFIG bits having a shipped value of 0b01 (section&nbsp;6.6.3.1)&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ddev_2-1648493228193.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/175033i36B9FEE2074EFDD9/image-size/medium?v=v2&amp;px=400" role="button" title="ddev_2-1648493228193.png" alt="ddev_2-1648493228193.png" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">ddev_2-1648493228193.png</span></span></P><P>The SEC_CONFIG bits on my board, however, are not reading 0b01, but instead reading 0b00.&nbsp;</P><P>I have tried reading the&nbsp;<SPAN>OCOTP_BOOT_CFG0 register, which the SEC_CONFIG bits are within, from Linux user space:&nbsp;<BR /></SPAN></P><LI-CODE lang="markup">~# cat /sys/fsl_otp/HW_OCOTP_BOOT_CFG0 0x0</LI-CODE><P>...and from the u-boot shell:</P><LI-CODE lang="markup">=&gt; fuse read 1 3 Reading bank 1: Word 0x00000003: 00000000</LI-CODE><P><BR />As you can see, this register reads all zeros using both methods, which suggests that the SEC_CONFIG fuse bit documented as being blown on ship isn't actually blown. Does anyone have an explanation for this? Is this a known discrepancy between the reference manual and the hardware? Or is it possible I have defective hardware?</P><P>I have experienced this on two i.MX7's at time of writing.&nbsp;<BR /><BR /></P><P>&nbsp;</P> Mon, 28 Mar 2022 19:07:08 GMT ddev 2022-03-28T19:07:08Z https://community.nxp.com/t5/i-MX-Processors/i-MX7-HAB-SEC-CONFIG-bits-all-read-zero/m-p/1434984#M188693 <P>Greetings. I have been trying to learn how to configure HAB on an i.MX7 and have came across a confusing observation regarding the SEC_CONFIG bits.&nbsp;&nbsp;<BR />The reference manual describes the SEC_CONFIG bits having a shipped value of 0b01 (section&nbsp;6.6.3.1)&nbsp;</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="ddev_2-1648493228193.png" style="width: 400px;"><img src="https://community.nxp.com/t5/image/serverpage/image-id/175033i36B9FEE2074EFDD9/image-size/medium?v=v2&amp;px=400" role="button" title="ddev_2-1648493228193.png" alt="ddev_2-1648493228193.png" /><span class="lia-inline-image-caption" onclick="event.preventDefault();">ddev_2-1648493228193.png</span></span></P><P>The SEC_CONFIG bits on my board, however, are not reading 0b01, but instead reading 0b00.&nbsp;</P><P>I have tried reading the&nbsp;<SPAN>OCOTP_BOOT_CFG0 register, which the SEC_CONFIG bits are within, from Linux user space:&nbsp;<BR /></SPAN></P><LI-CODE lang="markup">~# cat /sys/fsl_otp/HW_OCOTP_BOOT_CFG0 0x0</LI-CODE><P>...and from the u-boot shell:</P><LI-CODE lang="markup">=&gt; fuse read 1 3 Reading bank 1: Word 0x00000003: 00000000</LI-CODE><P><BR />As you can see, this register reads all zeros using both methods, which suggests that the SEC_CONFIG fuse bit documented as being blown on ship isn't actually blown. Does anyone have an explanation for this? Is this a known discrepancy between the reference manual and the hardware? Or is it possible I have defective hardware?</P><P>I have experienced this on two i.MX7's at time of writing.&nbsp;<BR /><BR /></P><P>&nbsp;</P> Mon, 28 Mar 2022 19:07:08 GMT https://community.nxp.com/t5/i-MX-Processors/i-MX7-HAB-SEC-CONFIG-bits-all-read-zero/m-p/1434984#M188693 ddev 2022-03-28T19:07:08Z