[iMX8MP] DDR4 data bit/byte swapping

khang_letruong — Sat, 19 Mar 2022 03:07:10 GMT

Dear Community,

We are about to design our custom iMX8M Plus based CPU board. We will use the same DDR4 memory (MT40A512M16LY-062E) as in the reference design of iMX8M Mini EVK (8MMINID4-EVK) but with half of capacity (8Gb or 1GB).

In the mentioned reference design, there seems to be bit-swapping of data lines between the DDRAM and the iMX8M Mini :

We also need to apply certain bit swapping to optimize the PCB layout and our own bit swapping would be different from above reference design. Therefore, I would like to know where to find the rules of DDR data bit/byte swapping applied for iMX8M Plus, please ? I found following article and application note (AN5097) which seem to be relevant : https://community.nxp.com/t5/Layerscape/AN5097-DDR4-Layout-Checklist-Clarification-for-LS1028A/td-p/1056006

AN5097 :

I would like to know if above rules should also be applied for the iMX8M Plus ?

Last question, what/where would take into account this bit swapping so that the DDRAM could work correctly : DDR RPA for the timing code generation or else where in u-Boot, please ?

Thanks in advance and best regards,

Khang

Re: [iMX8MP] DDR4 data bit/byte swapping

khang_letruong — Wed, 23 Mar 2022 14:39:39 GMT

Hi again, CC : @weidong_sun ,

I found the following discussion in which you said :

For DDR4, there is no restriction on the exchange of data bits, as you can see in this design files.

How can I interpret above statement correctly (i.e how can I configure this swapping correctly), please ? Seeing that there's no explicit BoardDataBusConfig tab in the MX8M_Plus_DDR4_RPA_v5.xlsx, but in MX8M_Plus_LPDDR4_RPA_v7.xlsx as below :

Thanks and best regards,

Khang.

i.MX Processors中的主题 [iMX8MP] DDR4 data bit/byte swapping

[iMX8MP] DDR4 data bit/byte swapping

Re: [iMX8MP] DDR4 data bit/byte swapping