Model Voltage error when simulating i.MX8 QM LPDDR4 interface with Hyperlynx

RichG — Mon, 14 Mar 2022 20:57:35 GMT

Hello. I have a design where I'm using the same LPDDR4 chips as the NXP eval board and in fact I have the same layout (pulled it in from the ODB++ files). It should work but I wanted to run a simulation to check. The models I'm using are:

i.MX8QM: imx8qm_29x29_rev1_25.ibs

MT53E768M32D4DT LPDDR4: z1am_200b-qdp_x32.ebd

The micron model within that ebd file is set to z1am_0p6V_st.ibs

When I set up the DDRx Batch Mode test in Hyperlynx, I get the following error:

There are nets with IBIS model voltage range compatibility issues:
Net(s): DDR_CH0_DM0..3, DDR_CH0_DQ0..31, DDR_CH1_DM0..3, DDR_CH1_DQ0..31
IBIS File: C:\Hyp\ADCMK5\Models\IMX8QM-IBIS\imx8qm_29x29_rev1_25.ibs
Selector/Model, Voltage: PDDRIO_PAD_DATA / DWC_D5MPL4_40 1.1V
Device(s): U1
IBIS File: C:\Hyp\ADCMK5\Models\MT53E768M32D4DT-053_ibis\z1am_0p6v_wt.ibs
Selector/Model, Voltage: DQ / DQ_PD40_ODT40_VOH50_4266 0.6V
Device(s): U0_EBD-U4, U2_EBD-U4

Am I trying to use the wrong models?

Thanks so much!

Rich

i.MX Processors中的主题 Model Voltage error when simulating i.MX8 QM LPDDR4 interface with Hyperlynx

Model Voltage error when simulating i.MX8 QM LPDDR4 interface with Hyperlynx