topic Re: Incorrect address mapping for imx8mp ddr4 with 16bit bus width (RPA) in i.MX Processors

Incorrect address mapping for imx8mp ddr4 with 16bit bus width (RPA)

michael_glembot — Mon, 14 Mar 2022 07:56:54 GMT

I just wanted to report an error in the Programming AID for the imx8mp with ddr4 for half bus width.

Here is our working DDR4 configuration:

There is an error in the address mapping. DDRC_ADDRMAP2 must be set to 0x00000007 but it is 0x00000707. That is because D77 is fixed. The field has no formula and always remains at 7 instead of 0.

Hopefully I will save others a few hours of debugging xD

Best, Michael

Re: Incorrect address mapping for imx8mp ddr4 with 16bit bus width (RPA)

jan_spurek — Mon, 14 Mar 2022 08:24:58 GMT

Hi Michael,

thank you for reporting this behavior. My initial analysis suggests that you are correct - could you please confirm that you have encountered calibration failures with the original configuration, which were resolved by the modification?

Thank you.

Best Regards,

Jan

Re: Incorrect address mapping for imx8mp ddr4 with 16bit bus width (RPA)

michael_glembot — Mon, 14 Mar 2022 10:10:59 GMT

Yes, exactly. That's why I reported the bug Calibration fails. Writing with the original configuration leads to several read/write errors in the test sequence, such as data for certain addresses being written in 2 places, again writing to other addresses had no effect at all.

Re: Incorrect address mapping for imx8mp ddr4 with 16bit bus width (RPA)

jan_spurek — Wed, 16 Mar 2022 10:54:43 GMT

Hi Michael,

ok, thank you for the details. I'll work on updating the RPA to correct the error.

Best Regards,

Jan