topic Re: Need support for SAI_RX2 issue in i.MX Processors

Need support for SAI_RX2 issue

LydieCDO — Thu, 03 Mar 2022 06:07:09 GMT

Hi NXP support,

We are working with IMXRT1176 and we are facing some issues.

Here is the context:

Using SAI1 on IMX1176, we are currently trying to use SAI1_RX2 to receive data from a tuner (SI47952) but we only get 0.
IMX is the master, and the tuner is slave.

GPIO DISP_B2_01 is configured as SAI1_RX2
If we monitor the connection, we can see that the signal is squeeze to 0 and almost 0V (see attached picture)

We have done the test of connecting the tuner to SAI1_RX0 (instead of SAI1_RX2) and it we did get the correct signal/data.
That means the issue is on the IMX side, we think this can be a pin config issue as the DISP_B2_01 is SAI1_RX2 and SAI1_TX2 but we don't know how to force RX mode.

Here some SAI1 registry dump during transfers
tcr1: 0x10 tcr2: 0x7000007 tcr3: 0x10000 tcr4: 0x10010f3b tcr5: 0xf0f0f00
rcr1: 0x10 rcr2: 0x47000007 rcr3: 0x40000 rcr4: 0x10010f1b rcr5: 0xf0f0f00

Do you have any idea to unlock this situation ?

Many thanks for your support.

Re: Need support for SAI_RX2 issue

rastislav_pavlanin — Thu, 03 Mar 2022 09:27:29 GMT

Hi @mike_susen ,

could you please take this request?

thanks.

regards

Re: Need support for SAI_RX2 issue

mike_susen — Thu, 03 Mar 2022 09:28:42 GMT

Hi @LydieCDO

Can you share the schematic and code with configuration?

Mike

Re: Need support for SAI_RX2 issue

eric_delanghe — Thu, 03 Mar 2022 10:12:40 GMT

Hello everyone.
Thanks for taking this issue

Here the schematic:
Tuner side:

IMX side:

Here the pin_mux from MCUExpresso config tools

IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03, /* GPIO_DISP_B2_00 is configured as SAI1_TX_DATA03 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02, /* GPIO_DISP_B2_01 is configured as SAI1_TX_DATA02 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01, /* GPIO_DISP_B2_02 is configured as SAI1_TX_DATA01 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK, /* GPIO_DISP_B2_03 is configured as SAI1_MCLK */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00, /* GPIO_DISP_B2_06 is configured as SAI1_RX_DATA00 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00, /* GPIO_DISP_B2_07 is configured as SAI1_TX_DATA00 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK, /* GPIO_DISP_B2_08 is configured as SAI1_TX_BCLK */ 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC, /* GPIO_DISP_B2_09 is configured as SAI1_TX_SYNC */ 0U); /* Software Input On Field: Input Path is determined by functionality */

And here the tx/rx config

SAI_GetClassicI2SConfig(&priv->I2SConfig, bit_width, is_stereo, priv->sai_chan); priv->I2SConfig.masterSlave = kSAI_Master; /* Note: See 58.3.2.1 Synchronous mode */ priv->I2SConfig.channelMask = kSAI_Channel0Mask; priv->I2SConfig.syncMode = kSAI_ModeAsync; SAI_TransferTxSetConfigEDMA(priv->sai, &(priv->txHandle), &priv->I2SConfig); priv->oneTxFrame = priv->txHandle.count * priv->txHandle.bytesPerFrame; priv->I2SConfig.channelMask = kSAI_Channel2Mask; priv->I2SConfig.syncMode = kSAI_ModeSync; SAI_TransferRxSetConfigEDMA(priv->sai, &(priv->rxHandle), &priv->I2SConfig); priv->oneRxFrame = priv->rxHandle.count * priv->rxHandle.bytesPerFrame; /* set bit clock divider */ /* Divide Root_SAIX clock (mclk) to bclk */ SAI_TxSetBitClockRate(priv->sai, clock_rate, sampling_rate, bit_width, nb_channel); SAI_RxSetBitClockRate(priv->sai, clock_rate, sampling_rate, bit_width, nb_channel);

Is it what you needed ?

Thanks again

Re: Need support for SAI_RX2 issue

mike_susen — Thu, 03 Mar 2022 12:22:44 GMT

Hi @eric_delanghe

I've checked configuration with Reference Manual and Pin tool and everything looks correct. Output from tuner has 3-state, Hi-Z, is there any internal pull-up inside tuner? it looks that there is greater pull-down what I see from oscilloscope image.

Mike

Re: Need support for SAI_RX2 issue

eric_delanghe — Thu, 03 Mar 2022 12:41:09 GMT

Hello @mike_susen

I'll ask tuner team for this but I'm not sure if this is related because if we connect the DOUT0(tuner) on SAI1_RX0(imx) the transfer work correctly.

Best regards,
Eric

Re: Need support for SAI_RX2 issue

mike_susen — Thu, 03 Mar 2022 13:28:45 GMT

Hi @eric_delanghe

are you sure that you not accessing the GPIO registers on this pin? It is not possible to have hard pull-down in this case.

Edit: DISP_B2_01 has internal PD turned on instedad of DISP_B2_06 which has HighZ mode. try to tune SW_PAD_CTL_PAD_GPIO_DISP_B2_01 SW PAD Control
Register (SW_PAD_CTL_PAD_GPIO_DISP_B2_01) to disable PD or switch to HighZ.

Mike

Re: Need support for SAI_RX2 issue

eric_delanghe — Mon, 07 Mar 2022 10:18:08 GMT

Hello @mike_susen ,

Thanks for your support
Also sorry for this late answer, I was busy on something else.

I've done the test and nothing changed.

I use NXP Config tool to generate the following line

IOMUXC_SetPinConfig( IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02, /* GPIO_DISP_B2_01 PAD functional properties : */ 0x02U); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: high drive strength Pull / Keep Select Field: Pull Disable, Highz Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled Domain write protection: Both cores are allowed Domain write protection lock: Neither of DWP bits is locked */

I tried with the following values

0x0	default
0x2	high drive strength
0x4	HIGHZ
0x6	HIGHZ, high drive strength

But it never worked.

Any other idea ?
Best regards,
Eric

Re: Need support for SAI_RX2 issue

eric_delanghe — Mon, 07 Mar 2022 10:19:48 GMT

Also you said that " It is not possible to have hard pull-down in this case."

We already tried to remove it and it does not help

Re: Need support for SAI_RX2 issue

Aubineau_FAE — Tue, 08 Mar 2022 08:50:32 GMT

Hi,

Can you confirm you see the signal disappearing if you do the measures on the 2 sides of the resistor, see below:

I have modified the SDK code and configured the pin as below:

 IOMUXC_SetPinMux(
IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02, /* GPIO_DISP_B2_01 is configured as SAI1_TX_DATA02 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03, /* GPIO_DISP_B2_00 is configured as SAI1_TX_DATA03 */
0U); /* Software Input On Field: Input Path is determined by functionality */

and measured the voltage on the switch:

And I see (logic analyser) no contention if I toggle the switch.

Did you check the IOMUX register is configured as expected with a JTAG probe?

Vincent

Re: Need support for SAI_RX2 issue

mike_susen — Tue, 08 Mar 2022 09:50:15 GMT

Hi @eric_delanghe

what about GPIO_DISP_B2_00? do you see same behavior also on tis pin?

Mike

Re: Need support for SAI_RX2 issue

eric_delanghe — Tue, 08 Mar 2022 09:57:46 GMT

Hello,

I just tried and get the same result on both side of R4261
Also I use gdb to check and registers are right.

Best regards,
Eric

Re: Need support for SAI_RX2 issue

eric_delanghe — Tue, 08 Mar 2022 10:01:50 GMT

Hello @mike_susen ,

We don't actually have DAB feature implemented.

But I'll ask hardware guys to patch my board to get FM data on GPIO_DISP_B2_00.

I will also ask hardware guys to connect the microphone (currently GPIO_DISP_B2_06) on GPIO_DISP_B2_01.

Best regards,

Eric

Re: Need support for SAI_RX2 issue

Aubineau_FAE — Tue, 08 Mar 2022 12:04:58 GMT

Hi,

But what is the value of R4261? it is O or another value, it is to ensure the i.MX force the pin to 0V.

Vincent

Re: Need support for SAI_RX2 issue

eric_delanghe — Tue, 08 Mar 2022 13:10:35 GMT

Hi again,

R4261 is a 0ohm, it's here to cut the lane and re-route if something goes wrong in the design.

Best regards,
Eric

Re: Need support for SAI_RX2 issue

Aubineau_FAE — Tue, 08 Mar 2022 15:46:01 GMT

Hi,

OK, so if an th RT is driving its pin low it cannot really be detected as it is a direct short circuit.

If you configure this pin as a GPIO, in input mode, do you still have the issue?:

Vincent

Re: Need support for SAI_RX2 issue

kerryzhou — Wed, 09 Mar 2022 04:02:38 GMT

Hi @LydieCDO ,

Please also try to modify your pinmux like this:

IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03, /* GPIO_DISP_B2_00 is configured as SAI1_TX_DATA03 */ 1U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02, /* GPIO_DISP_B2_01 is configured as SAI1_TX_DATA02 */ 1U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01, /* GPIO_DISP_B2_02 is configured as SAI1_TX_DATA01 */ 1U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK, /* GPIO_DISP_B2_03 is configured as SAI1_MCLK */ 1U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00, /* GPIO_DISP_B2_06 is configured as SAI1_RX_DATA00 */ 1U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00, /* GPIO_DISP_B2_07 is configured as SAI1_TX_DATA00 */ 1U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK, /* GPIO_DISP_B2_08 is configured as SAI1_TX_BCLK */ 1U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC, /* GPIO_DISP_B2_09 is configured as SAI1_TX_SYNC */ 1U); /* Software Input On Field: Input Path is determined by functionality */

Our SDK SAI code also set the software input on field as 1, you can try it on your side, whether your SAI receive still have issues or not.

Any updated information, just kindly let us know.

Best Regards,

Kerry

Re: Need support for SAI_RX2 issue

eric_delanghe — Thu, 10 Mar 2022 16:43:08 GMT

Hello,

If I configure DISP_B2_01 as GPIO5_02 the level is correct on the lane !
That means the issue come from the SAI configuration.

There is this diagram in the SAI documentation.

TX_DATA2 is used for sai_rxdata2 if "obe" is 0 but there is no information about this "obe". My thought was that it is configured by register TCR4 on bits TCE "Transmit Channel Enable"
And as I posted TCR4 is 0x10010f3b so TCE is 0x1 (TX0 enable, other are disabled)

Any information about that ?

Re: Need support for SAI_RX2 issue

eric_delanghe — Thu, 10 Mar 2022 16:49:45 GMT

Hello,

I just tried with a pinmux configured like this and nothing changed.

Do you know if there is anything to do on the SAI registers ?

Best regards,
Eric

Re: Need support for SAI_RX2 issue

kerryzhou — Fri, 11 Mar 2022 03:42:35 GMT

Hi @eric_delanghe ,

Thanks for your effort.

GPIO_DISP_B2_01 is also the BT_CFG[7], and in the MIMXRT1170-EVK board, it connect to the ground through the 47K resistor:

If no external input, it will be 0 in default.

Can you please test it like this:

I. disconnect your external wave to connect the board,

2 reset or POR,

3. after it boot, then connect your external SAI1_RXD[2], and check the wave, whether your external SAI can input the data to the RXD[2]?

If you still have issues, can you reproduce the issues on the NXP MIMXRT1170-EVK board, then I can help you to test it on my side.

Best Regards,

Kerry