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    <title>topic LPDDR4 configuration for IMX8M Quad in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-configuration-for-IMX8M-Quad/m-p/1419991#M187534</link>
    <description>&lt;P&gt;Hello,&lt;BR /&gt;I am using below part numbers.&lt;BR /&gt;1. LPDDR4 of Micron part no. MT53D512M32D2DS-046 IT:D with config 512M32 i.e. size 16Gb&lt;BR /&gt;2. IMX8M-Quad&lt;BR /&gt;Custom H/w interface: 32 DQ lines of IMX8M-Quad to interface with 2 channels of LPDDR4 using two CS0_A, CS0_B as we are using 512M32 [Note: CS1_A, CS1_B: Added in H/w for future]&lt;/P&gt;&lt;P&gt;We are using below NXP tools and guidelines&lt;BR /&gt;1. MX8M_LPDDR4_RPA_v30.xlsx - &lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8M-m850D-DDR-Register-Programming-Aid-RPA/ta-p/1172441" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8M-m850D-DDR-Register-Programming-Aid-RPA/ta-p/1172441&lt;/A&gt;&lt;BR /&gt;2. MSCALE_DDR_Tool_User_Guide.pdf (IMX Rev. V2.0.0 1/23/2021) - &lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467&lt;/A&gt;&lt;/P&gt;&lt;P&gt;[QUERY-1]:&lt;BR /&gt;We feel bit unclear about parameter 'Number of Channels' and 'Total DRAM Density'. In our scenario, we set below parameters using datasheet of MT53D512M32D2DS-046 IT:D (size 16Gb)&lt;BR /&gt;a. Bus width : 32&lt;BR /&gt;b. Number of Channels (Auto-compute) : 2&lt;BR /&gt;c. Density per channel per chip select (Gb): 8 Gb&lt;BR /&gt;d. Number of Chip Selects used : 2&lt;BR /&gt;e. Total DRAM density (Gb)(Auto-compute) : 32&lt;BR /&gt;f. Clock Cycle Freq (MHz) : 2133 (because of speed-grade 046)&lt;BR /&gt;g. Clock Cycle Time (ns) (Auto-compute) : 0.468823254&lt;BR /&gt;&lt;BR /&gt;In DDR tool user guide, parameter 'Number of Channels per chip select' is present.&lt;BR /&gt;Request you please guide on above unclear parameters 'Number of Channels' and 'Total DRAM Density' and validate the correctness.&lt;BR /&gt;&lt;BR /&gt;[QUERY-2]:&lt;BR /&gt;In MSCALE_DDR_Tool.exe,&lt;BR /&gt;a. Target drop-down has 4 options. In our case, we have MIMX8-Quad so we selected 'MX8M'&lt;BR /&gt;b. Clock drop-down has 4 options (including Default). Please guide which one to select&lt;BR /&gt;c. Density has list in drop-down. Please guide which one to select referring to part.e of QUERY-1&lt;/P&gt;</description>
    <pubDate>Sat, 26 Feb 2022 04:11:11 GMT</pubDate>
    <dc:creator>VJain</dc:creator>
    <dc:date>2022-02-26T04:11:11Z</dc:date>
    <item>
      <title>LPDDR4 configuration for IMX8M Quad</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-configuration-for-IMX8M-Quad/m-p/1419991#M187534</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;I am using below part numbers.&lt;BR /&gt;1. LPDDR4 of Micron part no. MT53D512M32D2DS-046 IT:D with config 512M32 i.e. size 16Gb&lt;BR /&gt;2. IMX8M-Quad&lt;BR /&gt;Custom H/w interface: 32 DQ lines of IMX8M-Quad to interface with 2 channels of LPDDR4 using two CS0_A, CS0_B as we are using 512M32 [Note: CS1_A, CS1_B: Added in H/w for future]&lt;/P&gt;&lt;P&gt;We are using below NXP tools and guidelines&lt;BR /&gt;1. MX8M_LPDDR4_RPA_v30.xlsx - &lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8M-m850D-DDR-Register-Programming-Aid-RPA/ta-p/1172441" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX8M-m850D-DDR-Register-Programming-Aid-RPA/ta-p/1172441&lt;/A&gt;&lt;BR /&gt;2. MSCALE_DDR_Tool_User_Guide.pdf (IMX Rev. V2.0.0 1/23/2021) - &lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467&lt;/A&gt;&lt;/P&gt;&lt;P&gt;[QUERY-1]:&lt;BR /&gt;We feel bit unclear about parameter 'Number of Channels' and 'Total DRAM Density'. In our scenario, we set below parameters using datasheet of MT53D512M32D2DS-046 IT:D (size 16Gb)&lt;BR /&gt;a. Bus width : 32&lt;BR /&gt;b. Number of Channels (Auto-compute) : 2&lt;BR /&gt;c. Density per channel per chip select (Gb): 8 Gb&lt;BR /&gt;d. Number of Chip Selects used : 2&lt;BR /&gt;e. Total DRAM density (Gb)(Auto-compute) : 32&lt;BR /&gt;f. Clock Cycle Freq (MHz) : 2133 (because of speed-grade 046)&lt;BR /&gt;g. Clock Cycle Time (ns) (Auto-compute) : 0.468823254&lt;BR /&gt;&lt;BR /&gt;In DDR tool user guide, parameter 'Number of Channels per chip select' is present.&lt;BR /&gt;Request you please guide on above unclear parameters 'Number of Channels' and 'Total DRAM Density' and validate the correctness.&lt;BR /&gt;&lt;BR /&gt;[QUERY-2]:&lt;BR /&gt;In MSCALE_DDR_Tool.exe,&lt;BR /&gt;a. Target drop-down has 4 options. In our case, we have MIMX8-Quad so we selected 'MX8M'&lt;BR /&gt;b. Clock drop-down has 4 options (including Default). Please guide which one to select&lt;BR /&gt;c. Density has list in drop-down. Please guide which one to select referring to part.e of QUERY-1&lt;/P&gt;</description>
      <pubDate>Sat, 26 Feb 2022 04:11:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-configuration-for-IMX8M-Quad/m-p/1419991#M187534</guid>
      <dc:creator>VJain</dc:creator>
      <dc:date>2022-02-26T04:11:11Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4 configuration for IMX8M Quad</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-configuration-for-IMX8M-Quad/m-p/1422992#M187783</link>
      <description>&lt;P&gt;Details you can refer to &lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/1104467&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 04 Mar 2022 02:16:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-configuration-for-IMX8M-Quad/m-p/1422992#M187783</guid>
      <dc:creator>Rita_Wang</dc:creator>
      <dc:date>2022-03-04T02:16:39Z</dc:date>
    </item>
    <item>
      <title>Re: LPDDR4 configuration for IMX8M Quad</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-configuration-for-IMX8M-Quad/m-p/1423500#M187834</link>
      <description>&lt;P&gt;In my post, i have mentioned same link and used as well. But i have specific query1 and query2. Any help will be appreciated.&lt;/P&gt;</description>
      <pubDate>Sat, 05 Mar 2022 11:00:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LPDDR4-configuration-for-IMX8M-Quad/m-p/1423500#M187834</guid>
      <dc:creator>VJain</dc:creator>
      <dc:date>2022-03-05T11:00:13Z</dc:date>
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