<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: IMX8MM PCIE  CLK OUT in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-PCIE-CLK-OUT/m-p/1416696#M187268</link>
    <description>&lt;P&gt;Hi，&lt;/P&gt;&lt;P&gt;I refer to that and write the corresponding register, but clk has no output.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;code:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;/* Configure the PHY to output the refclock via pad */&lt;BR /&gt;writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG061);&lt;BR /&gt;writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG062);&lt;BR /&gt;writel(AUX_PLL_REFCLK_SEL_SYS_PLL,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG063);&lt;BR /&gt;value = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;&lt;BR /&gt;writel(value | ANA_AUX_RX_TERM_GND_EN,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG064);&lt;BR /&gt;writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG065);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 21 Feb 2022 10:07:26 GMT</pubDate>
    <dc:creator>story</dc:creator>
    <dc:date>2022-02-21T10:07:26Z</dc:date>
    <item>
      <title>IMX8MM PCIE  CLK OUT</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-PCIE-CLK-OUT/m-p/1416310#M187228</link>
      <description>&lt;P&gt;Hello，&lt;/P&gt;&lt;P&gt;we are using imx8mm chip, bsp 5.4.3.&lt;/P&gt;&lt;P&gt;we need to use pcie to output 100mhhz clk, we see that evk all use other ic output, is there any related patch provided, I saw the forum by related posts, also The register test corresponding to the parameter setting, the unit cannot output clk.&lt;/P&gt;</description>
      <pubDate>Sun, 20 Feb 2022 14:30:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-PCIE-CLK-OUT/m-p/1416310#M187228</guid>
      <dc:creator>story</dc:creator>
      <dc:date>2022-02-20T14:30:19Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MM PCIE  CLK OUT</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-PCIE-CLK-OUT/m-p/1416372#M187237</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/109300"&gt;@story&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; please look at the following:&lt;/P&gt;
&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/imx8mm-pcie-ref-clock/m-p/994867" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors/imx8mm-pcie-ref-clock/m-p/994867&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Mon, 21 Feb 2022 02:36:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-PCIE-CLK-OUT/m-p/1416372#M187237</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2022-02-21T02:36:48Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MM PCIE  CLK OUT</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-PCIE-CLK-OUT/m-p/1416696#M187268</link>
      <description>&lt;P&gt;Hi，&lt;/P&gt;&lt;P&gt;I refer to that and write the corresponding register, but clk has no output.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;code:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;/* Configure the PHY to output the refclock via pad */&lt;BR /&gt;writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG061);&lt;BR /&gt;writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG062);&lt;BR /&gt;writel(AUX_PLL_REFCLK_SEL_SYS_PLL,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG063);&lt;BR /&gt;value = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;&lt;BR /&gt;writel(value | ANA_AUX_RX_TERM_GND_EN,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG064);&lt;BR /&gt;writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL,&lt;BR /&gt;imx8_phy-&amp;gt;base + IMX8MM_PCIE_PHY_CMN_REG065);&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 21 Feb 2022 10:07:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MM-PCIE-CLK-OUT/m-p/1416696#M187268</guid>
      <dc:creator>story</dc:creator>
      <dc:date>2022-02-21T10:07:26Z</dc:date>
    </item>
  </channel>
</rss>

