IMX8MP Setting SYS_PLL frequency

TerryBarnaby1 — Thu, 17 Feb 2022 10:52:50 GMT

I am adding support for a tp2855 video processing chip to a custom board. This requires 27 MHz from the GPIO1.15 pin using the IMX8MP_CLK_IPP_DO_CLKO2.

I have set the tp2855 device tree settings to have:

assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>;
assigned-clock-rates = <27000000>;

IMX8MP_SYS_PLL3_OUT does not appear to be used by anything else. When I do this I get 27.27 MHz presumably because the PLL3 is producing 600 Mhz and there is a simple integer divide going on.

To get better accuracy how do I set the PLL3's core frequency in the device tree or uboot or the kernel as I can't see where I can set this up ?

Re: IMX8MP Setting SYS_PLL frequency

TerryBarnaby1 — Mon, 21 Feb 2022 08:41:25 GMT

I have managed to sort this. It looks like the IMX8MP PLL frequencies are set in the u-boot file: arch/arm/mach-imx/imx8m/clock_imx8mm.c

There are some set PLL frequencies with appropriate PLL division register values in intpll_configure(). I added to this:

case MHZ(648):
  /* 24 * 324 / 3 / 2 ^ 2 */
  pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(324) | INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(2);
  break;

The PLL's have a pre integer divider, a feedback divider and an output divide by 2^n divider. Not sure on the recommended PLL operation frequency range.

Then in clock_init() I changed:

#ifdef DS200I_PLL3
  intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(648));
#else
if (is_imx8mn() || is_imx8mp())
  intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(600));
else
  intpll_configure(ANATOP_SYSTEM_PLL3, MHZ(750));
#endif

On my DS200i board PLL3 wasn't being used so I could happily change its default frequency. Now my IMX8MP_CLK_IPP_DO_CLKO2 is at 27 MHz.

Not sure if there is better device tree way of doing this.

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IMX8MP Setting SYS_PLL frequency

Re: IMX8MP Setting SYS_PLL frequency