topic Re: clock signal of IMX6Q does not output SPI device in i.MX Processors

clock signal of IMX6Q does not output SPI device

villager — Mon, 17 Jan 2022 06:12:12 GMT

Hello

I attached spi device to imx6q.

(spi dev was wired spi1)

pinmap is bellow

OLED_SCLK -----CSI0_DAT4

OLED_SDIN -----CSI0_DAT5

OLED_D_C/ -----CSI0_DAT6

OLED_CS/ -----CSI0_DAT7

CSI0_DAT4 ALT2 ECSPI1_SCLK

CSI0_DAT5 ALT ECSPI1_MOSI

CSI0_DAT6 ALT ECSPI1_MISO

CSI0_DAT7 ALT ECSPI1_SS0

dts is bellow

ecspi1: ecspi@02008000 {

#address-cells = <1>;

#size-cells = <0>;

compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";

reg = <0x02008000 0x4000>;

interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;

clocks = <&clks IMX6QDL_CLK_ECSPI1>,

<&clks IMX6QDL_CLK_ECSPI1>;

clock-names = "ipg", "per";

dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;

dma-names = "rx", "tx";

status = "disabled";

};

&ecspi1 {

fsl,spi-num-chipselects = <1>;

cs-gpios = <&gpio5 25 0>;

pinctrl-names = "default";

pinctrl-0 = <&pinctrl_ecspi1>;

/*status = "okay";*/

status = "okay";

spidev0: spi@0 {

#address-cells = <1>;

#size-cells = <1>;

compatible = "spidev";

reg = <0>;

spi-max-frequency = <2000000>;

};

pinctrl_ecspi1: ecspi1grp {

fsl,pins = <

MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1

MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1

MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1

MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x1b0b0

};

but clock signal does not output.

does my dts wrong?

or do I need to set additional setting?

With best regards,

villager

Re: clock signal of IMX6Q does not output SPI device

igorpadykov — Mon, 17 Jan 2022 08:49:30 GMT

Hi Villager

one can look at testing procedure on below link

https://variwiki.com/index.php?title=VAR-SOM-MX6_Yocto_Unit_Testing_V7#SPI

Best regards
igor

Re: clock signal of IMX6Q does not output SPI device

villager — Mon, 17 Jan 2022 09:02:11 GMT

hello igor,
thank you for your reply.

I already did spidev test and it didn't work properly,
so I took a check with an oscilloscope and found that the clock signal was not coming out.

best regards

villager

Re: clock signal of IMX6Q does not output SPI device

villager — Fri, 21 Jan 2022 02:11:57 GMT

thank you igor.

I haven't made any progress yet.
I dumped the register.
can you please check if this value is correct?

//mux setting
@0x20e0080(IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07), read_reg 0x5
@0x20e0394(IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07), read_reg 0x1b0b0
@0x20e0074(IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04), read_reg 0x2
@0x20e0078(IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05), read_reg 0x2
@0x20e007c(IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06), read_reg 0x2
@0x20e0388(IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04), read_reg 0x100b1
@0x20e038c(IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05), read_reg 0x100b1
@0x20e0390(IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06), read_reg 0x100b1
//spi settng
@0x2008008(ECSPI1_CONREG), read_reg 0x7020f1
@0x200800c(ECSPI1_CONFIGREG), read_reg 0x100
//clock setting
@0x20c4060(CCM_CCOSR), read_reg 0xe017b

Re: clock signal of IMX6Q does not output SPI device

Yuri — Fri, 18 Feb 2022 09:30:37 GMT

@villager
Hello,

I looked at Your mux settings. As I see IOMUXC registers addresses do not correspond i.MX6Q.
They are for i.MX6S/DL.
What is exact i.MX6 part number on Your board?

Regards,
Yuri.

Re: clock signal of IMX6Q does not output SPI device

villager — Sun, 20 Feb 2022 23:30:42 GMT

HELLO @Yuri

my EVB is i.MX6Q, real target is i.MX6S/DL
There is not much difference between these two, so I wrote them in confusion.

The reason the clock does not tx is because there is no SPI clock setting.
According to the chip manual (IMX6SDLRM Rev. 1, 04/2013),
the PLL should be divided by /8 and /1.

After booting, I set the following additional settings in linux application,

and the clock signal came out normally.

/* 2nd : change clock Register (CCM_CCOSR) */ /* chip manual : 18.6.21 CCM Clock Output Source Register (CCM_CCOSR) */ setting=0x0; #define CLK01_SEL ( 1<<3 | 0<<2 | 1<<1 | 1<<0) //1011 ahb_clk_root #define CLK01_DIV ( 1<<6 | 1<<5 | 1<<4) //111 divide by 8 #define CLK01_EN ( 0<<7 ) #define CLK_OUT_SEL ( 1<<8 ) #define CLK02_SEL ( 0<<20 | 1<<19 | 1<<18 | 1<<17 | 0<<16) //01110 osc_clk #define CLK02_DIV ( 0<<23 | 0<<22 | 0<<21) //111 divide by 8 #define CLK02_EN ( 0<<24 ) setting=(setting | CLK01_SEL); setting=(setting | CLK01_DIV); setting=(setting | CLK01_EN); setting=(setting | CLK_OUT_SEL); setting=(setting | CLK02_SEL); setting=(setting | CLK02_DIV); setting=(setting | CLK02_EN); read_reg=0; mmap_ioctl((unsigned long)&CCM_CCOSR, &read_reg, MMAP_RD); if(read_reg != setting) { printf("@%p(CCM_CCOSR) change property 0x%x->0x%x\n" , (void *)&CCM_CCOSR, read_reg, setting); mmap_ioctl((unsigned long)&CCM_CCOSR, &setting, MMAP_WR); }

thank you.