<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Big latency in i2c writes in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1414433#M187063</link>
    <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/1941"&gt;@Yuri&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;thank you for your answer. I measured the i2c timings. For a whole i2c reg write it needs 115&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;s, this seems to be okay. And then there is pause of 176&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;s for the next SCL burst.&lt;/P&gt;&lt;P&gt;Can we optimize this?&lt;/P&gt;</description>
    <pubDate>Wed, 16 Feb 2022 12:31:04 GMT</pubDate>
    <dc:creator>Eximius</dc:creator>
    <dc:date>2022-02-16T12:31:04Z</dc:date>
    <item>
      <title>Big latency in i2c writes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1413072#M186975</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I'm doing some latency tests with the i2c communication on the Imx8m Plus, measuring by software the wall time of the i2cwrite function (i2c_smbus_write_byte_data).&lt;/P&gt;&lt;P&gt;When setting the clock speed to 100KHz, single writes take about 500&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;&lt;/SPAN&gt;s. With clock @400KHz, about 300&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;&lt;/SPAN&gt;s.&lt;/P&gt;&lt;P&gt;I was expecting a single write to take something like 280&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;&lt;/SPAN&gt;s (@100KHz) or 70&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;&lt;/SPAN&gt;s (@400KHz). So I always get an overhead of about 220&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;&lt;/SPAN&gt;s, independent of the clock frequency.&lt;/P&gt;&lt;P&gt;I also tried other I2C Buses and other I2C slaves, I always get a similar latency.&lt;/P&gt;&lt;P&gt;Can you advise how we can get closer of the 320kbps (Imx8m specification)?&lt;/P&gt;</description>
      <pubDate>Mon, 14 Feb 2022 12:15:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1413072#M186975</guid>
      <dc:creator>Eximius</dc:creator>
      <dc:date>2022-02-14T12:15:28Z</dc:date>
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    <item>
      <title>Re: Big latency in i2c writes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1413654#M187017</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/191759"&gt;@Eximius&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; Is it possible to verify (using oscilloscope) if the latency takes place &lt;BR /&gt;because of incorrect I2C frequency setting or because of delays between &lt;BR /&gt;I2C bursts (with correct frequency)? The recent is quite expectable -&lt;BR /&gt;taking into account internal i.MX8 complexity.&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri.&lt;/P&gt;</description>
      <pubDate>Tue, 15 Feb 2022 11:12:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1413654#M187017</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2022-02-15T11:12:15Z</dc:date>
    </item>
    <item>
      <title>Re: Big latency in i2c writes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1414433#M187063</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/1941"&gt;@Yuri&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;thank you for your answer. I measured the i2c timings. For a whole i2c reg write it needs 115&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;s, this seems to be okay. And then there is pause of 176&lt;SPAN class=""&gt;µ&lt;/SPAN&gt;s for the next SCL burst.&lt;/P&gt;&lt;P&gt;Can we optimize this?&lt;/P&gt;</description>
      <pubDate>Wed, 16 Feb 2022 12:31:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1414433#M187063</guid>
      <dc:creator>Eximius</dc:creator>
      <dc:date>2022-02-16T12:31:04Z</dc:date>
    </item>
    <item>
      <title>Re: Big latency in i2c writes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1414961#M187097</link>
      <description>&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/191759"&gt;@Eximius&lt;/a&gt;&amp;nbsp;&lt;BR /&gt;Hello,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&amp;nbsp; generally it would be possible to use DMA with I2C, but NXP Linux does not support it.&lt;/P&gt;
&lt;P&gt;&amp;nbsp; Nevertheless, according to i.MX Linux Reference Manual:&lt;/P&gt;
&lt;P&gt;"It is strongly recommended not to use I2C SDMA mode when sending small amounts of data. &lt;BR /&gt;If there is a special case that needs to send a large amount of I2C data, contact NXP Pro-support &lt;BR /&gt;to get the patchset."&lt;/P&gt;
&lt;P&gt;Regards,&lt;BR /&gt;Yuri&lt;/P&gt;</description>
      <pubDate>Thu, 17 Feb 2022 04:14:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1414961#M187097</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2022-02-17T04:14:29Z</dc:date>
    </item>
    <item>
      <title>Re: Big latency in i2c writes</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1415056#M187107</link>
      <description>&lt;P&gt;SDMA support for I2C requires SDMA firmware 3.6/4.6. It is included in &lt;A href="https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.12.bin" target="_self"&gt;firmware-imx-8.12.bin&lt;/A&gt;. Additionally you need some small changes in the Linux drivers.&lt;/P&gt;&lt;P&gt;For larger transfers (I2C eeprom), I could increase performance by about 20%. For small transfers, I don't expect much benefit.&lt;/P&gt;&lt;P&gt;regards,&lt;BR /&gt;Christian&lt;/P&gt;</description>
      <pubDate>Thu, 17 Feb 2022 07:30:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Big-latency-in-i2c-writes/m-p/1415056#M187107</guid>
      <dc:creator>ceggers</dc:creator>
      <dc:date>2022-02-17T07:30:38Z</dc:date>
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  </channel>
</rss>

